An enhanced test generator for capacitance induced crosstalk delay faults

Proceedings of the Asian Test Symposium

Volumn 2003-January, Issue , 2003, Pages 174-177

  Sinha, A ^a   Gupta, S K ^a   Breuer, M A ^a  

^a University of Southern California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; CROSSTALK; HAZARDS; RECONFIGURABLE HARDWARE;

CAPACITIVE CROSSTALK; CROSSTALK DELAY FAULTS; DELAY MODELING; FUNCTIONAL ERRORS; LOGIC VALUES; REQUIRED TIME; SOLUTION SPACE; TEST GENERATION METHODOLOGY;

TESTING;

EID: 47349128680     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2003.1250805     Document Type: Conference Paper

References (4)

1. L. C. Chen, S. K. Gupta, and M. A. Breuer: A new gate delay model for simultaneous switching and its applications, Proc. of Design Automation Conference, 2001, pp. 289-294.
2. W.-Y. Chen: Test Generation for Crosstalk Noise in VLSI circuits, Ph.D. Dissertation, Dept. of EE-Systems, Univ. Of Southern California, 2000.
3. I-D. Huang, S.K. Gupta, and M. A. Breuer: Accurate and efficient static timing analysis with crosstalk, Proc. of Intl. Conf. on Computer Design, 2002, pp. 265-272.
4. L. C. Chen, S. K. Gupta, and M. A. Breuer: TA-PSV: Timing analysis for partially specified vectors, Journal of Electronic Testing: Theory and Applications, vol. 18, no. 1, pp. 73-78, 2001.