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Volumn , Issue , 2006, Pages 1280-1283

Wave pipelining using self reset logic

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC CMOS; HIGH-SPEED DATA; INTERNATIONAL CONFERENCES; NOVEL DESIGN; SELF-RESET LOGIC (SRL); WAVE PIPELINING;

EID: 47349105505     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2006.379715     Document Type: Conference Paper
Times cited : (1)

References (10)
  • 1
    • 47349085091 scopus 로고    scopus 로고
    • Wave Pipelining with Self Reset Logic
    • Doctoral Dissertation, Santa Clara University, CA
    • Miguel Litvin. "Wave Pipelining with Self Reset Logic". Doctoral Dissertation, Santa Clara University, CA, 2005.
    • (2005)
    • Litvin, M.1
  • 2
    • 16444361841 scopus 로고    scopus 로고
    • Self Reset Logic for Fast Arithmetic Applications
    • April
    • Miguel Litvin and Samiha Mourad. "Self Reset Logic for Fast Arithmetic Applications". IEEE Transactions on VLSI Systems, Vol. 13, No. 4, April 2005.
    • (2005) IEEE Transactions on VLSI Systems , vol.13 , Issue.4
    • Litvin, M.1    Mourad, S.2
  • 3
    • 0347239890 scopus 로고
    • Wave Pipelining Theoretical & Practical Issues in CMOS
    • Doctoral Dissertation, Stanford, CA
    • E.F. Klass, "Wave Pipelining Theoretical & Practical Issues in CMOS" Doctoral Dissertation, Stanford, CA, 1994.
    • (1994)
    • Klass, E.F.1
  • 4
    • 0026995327 scopus 로고    scopus 로고
    • W. Lam, Brayton and Sangiovanni-Vincentelli, Valid Clocking in Wavepipelined Circuits Proceedings of ICCAD '92, Santa Clara, CA, Nov. 1992, pp. 518-525.
    • W. Lam, Brayton and Sangiovanni-Vincentelli, "Valid Clocking in Wavepipelined Circuits Proceedings of ICCAD '92, Santa Clara, CA, Nov. 1992, pp. 518-525.
  • 6
    • 0032647363 scopus 로고    scopus 로고
    • A 500-MHz, 32-Word × 64-Bit, Eight-Port Self-Resetting CMOS Register File
    • Jan
    • Hwang, Joshi, Henkels, "A 500-MHz, 32-Word × 64-Bit, Eight-Port Self-Resetting CMOS Register File", IEEE Journal of Sol.State Circ. vol 34, No 1, Jan 1999.
    • (1999) IEEE Journal of Sol.State Circ , vol.34 , Issue.1
    • Hwang1    Joshi2    Henkels3
  • 7
    • 47349132060 scopus 로고    scopus 로고
    • Reset Logic Circuit and Method
    • U.S. Patent 5430399
    • Dennis Wendell, "Reset Logic Circuit and Method". U.S. Patent 5430399.
    • Wendell, D.1
  • 8
    • 0027697031 scopus 로고
    • A 6ns Cycle, 256-Kb Cache Memory and Memory Management Unit
    • Nov
    • Raymond Heald, John Hoist, "A 6ns Cycle, 256-Kb Cache Memory and Memory Management Unit", IEEE Journal of Solid State Circuits, Vol. 28, No. 11, Nov. 1993.
    • (1993) IEEE Journal of Solid State Circuits , vol.28 , Issue.11
    • Heald, R.1    Hoist, J.2
  • 9
    • 0032204698 scopus 로고    scopus 로고
    • 64-KByte Sum-Addressed-Memory Cache with 1.6-ns Cycle and 2.6-ns Latency
    • Nov
    • Raymond Heald, Ken Shin, et al. "64-KByte Sum-Addressed-Memory Cache with 1.6-ns Cycle and 2.6-ns Latency", IEEE Journal of Solid State Circuits, Vol. 33, No. 11, Nov. 1998.
    • (1998) IEEE Journal of Solid State Circuits , vol.33 , Issue.11
    • Heald, R.1    Shin, K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.