Self-reset logic for fast arithmetic applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 4, 2005, Pages 462-475

  Litvin, Miguel E ^a   Mourad, Samiha ^a  

^a Santa Clara University   (United States)

Author keywords

Asynchronous circuits; Dual rail logic; Dynamic logic; Pulsed logic; Self reset logic (SRL); Self timed circuits

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION; SIGNAL GENERATORS; THERMAL EFFECTS;

ASYNCHRONOUS CIRCUITS; DUAL-RAIL LOGIC; DYNAMIC LOGIC; SELF-RESET LOGIC (SRL); SELF-TIMED CIRCUITS;

LOGIC GATES;

EID: 16444361841     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.842921     Document Type: Article

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