Transaction based modeling and verification of hardware protocols

Proceedings - Formal Methods in Computer Aided Design, FMCAD 2007

Volumn , Issue , 2007, Pages 53-61

  Chen, Xiaofang ^a   German, Steven M ^b   Gopalakrishnan, Ganesh ^a  

^a Department of Electrical and Computer Engineering

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATED SYNTHESIS; CACHE COHERENCE; CLOCK CYCLES; FORMAL THEORY; HIGH-PERFORMANCE CONTROLLERS; INTERLEAVING SEMANTICS; MODULAR VERIFICATION; NON-TRIVIAL; TRANSITION (JEL CLASSIFICATIONS:E52 ,E41 ,E31);

COMPUTER AIDED DESIGN; COMPUTER CONTROL SYSTEMS; COMPUTER HARDWARE; INFORMATION THEORY; SPECIFICATIONS;

FORMAL METHODS;

EID: 47349097031     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FAMCAD.2007.20     Document Type: Conference Paper

References (22)

1. L. Yang, D. Gao, J. Mostoufi, R. Joshi, and P. Loewenstein, "System design methodology of UltraSPARC-I," in Design Automation Conference, 1995.
2. S. M. German, "Formal design of cache memory protocols in IBM," in Formal Methods in System Design, 2003.
3. C. T. Chou, S. M. German, and G. Gopalakrishnan, "Tutorial on specification and verification of shared memory protocols and consistency models," in Formal Methods in Computer-Aided Design, 2004.
4. B. Batson and L. Lamport, "High-level specifications: Lessons from industry," in Formal Methods for Components and Objects, 2002.
5. D. L. Dill, A. J. Drexler, A. J. Hu, and C. H. Yang, "Protocol verification as a hardware design aid," in IEEE Intl. Conference on Computer Design: VLSI in Computers and Processors, 1992.
6. L. Lamport, Specifying Systems: The TLA+ Language and Tools for Hardware and Software Engineers. Addison-Wesley, 2002.
7. S. M. German, personal Communication.
8. S. German and G. Janssen, "A tutorial example of a cache memory protocol and RTL implementation," IBM Research Report, RC23958, Tech. Rep., 2006.
9. S. German, "Tutorial on verification of distributed cache memory protocols," in Formal Methods in Computer Aided Design, 2004.
10. N. Mellergaard and J. Staunstrup, "Tutorial on design verification with synchronized transitions," in International Conference on Theorem Provers in Circuit Design, 1994.
11. J. Staunstrup, A Formal Approach to Hardware Design. Kluwer Academic Publishers, 1994.
12. K. M. Chandy and J. Misra, Parallel Program Design: A Foundation. Addison-Wesley, 1988.
13. Arvind and X. Shen, "Using term rewriting systems to design and verify processors," in IEEE Micro, 1999.
14. Arvind, R. Nikhil, D. Rosenband, and N. Dave, "High-level synthesis: An essential ingredient for designing complex ASICs," in International Conference on Computer Aided Design, 2004.
15. J. Hoe and Arvind, "Hardware synthesis from term rewriting systems," in International Conference on Very Large Scale Integration: Systems on a Chip, 1999.
16. Http://www.bluespec.com/.
17. S. Park, "Computer assisted analysis of multiprocessor memory systems," Ph.D. dissertation, Stanford University, 1996.
18. C. Jones, "Tentative steps towards a development method for interfering programs," ACM Transactions on Programming Languages and Systems, vol. 5, no. 4, pp. 596-616, 1983.
19. K. McMillan, "A compositional rule for hardware design refinement," in Computer Aided Verification, 1997.
20. S. Hazelhurst and C. H. Seger, "Symbolic trajectory evaluation," in Formal Hardware Verification - Methods and Systems in Comparison, 1996.
21. S. Owicki and D. Gries, "Verifying properties of parallel programs: An axiomatic approach," Communications of the ACM, vol. 19, no. 5, pp. 279-284, 1994.
22. I. Beer, S. Ben-David, C. Eisner, D. Geist, L. Gluhovsky, T. Heyman, A. Landver, P. Paanah, Y. Rodeh, G. Ronin, and Y. Wolfsthal, "Rulebase: Model checking at IBM," in Intl. Conference on Computer-Aided Verification, 1997.