Sampling from the multivariate Gaussian distribution using reconfigurable hardware

Proceedings 2007 IEEE Symposium on Field-Programme Custom Computing Machines, FCCM 2007

Volumn , Issue , 2007, Pages 3-12

  Thomas, David B ^a   Luk, Wayne ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GAUSSIAN DISTRIBUTION; MATRIX ALGEBRA; RANDOM PROCESSES; VALUE ENGINEERING; VECTORS;

COMPUTATIONAL CHALLENGES; CORRELATION MATRIX; FPGA BASED SIMULATIONS; GENERATION RATE; HARDWARE ARCHITECTURE; MULTIVARIATE GAUSSIAN DISTRIBUTIONS; MULTIVARIATE TIME SERIES; SOFTWARE SIMULATION;

RECONFIGURABLE HARDWARE;

EID: 47349096982     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2007.55     Document Type: Conference Paper

References (18)

1. Advanced Micro Devices. AMD Core Math Library (ACML), 2006.
2. Altera Corporation. Stratix II Device Handbook, Volume 1, 2005.
3. D. R. Barr and N. L. Slezak. A comparison of multivariate normal generators. Commun. ACM, 15(12):1048-1049, 1972.
4. F. Black and M. S. Scholes. The pricing of options and corporate liabilities. Journal of Political Economics, 81:637-659, 1973.
5. M. deLorimier and A. DeHon. Floating-point sparse matrix-vector multiply for FPGAs. In Proc. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 75-85. ACM Press, 2005.
6. M. George and P. Alfke. Linear feedback shift registers in Virtex devices. Technical report, Xilinx Inc., 2001.
7. X. Inc. Additive white gaussian noise (AWGN) core. CoreGen documentation file, 2002.
8. J.-W. Jang, S. B. Choi, and V. K. Prasanna. Energy- and time-efficient matrix multiplication on FPGAs. IEEE Transactions on VLSI Systems, 13(11):1305-1319, 2005.
9. D.-U. Lee, W. Luk, J. D. Villasenor, and P. Y. Cheung. A gaussian noise generator for hardware-based simulations. IEEE Transactions On Computers, 53(12):1523-1534, december 2004.
10. D.-U. Lee, W. Luk, J. D. Villasenor, G. Zhang, and P. H. Leong. A hardware gaussian noise generator using the wallace method. IEEE Transactions on VLSI Systems, 13(8):911-920, 2005.
11. B. Shackleford, M. Tanaka, R. J. Carter, and G. Snider. FPGA implementation of neighborhood-of-four cellular automata random number generators. In Proc. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 106-112, New York, USA, 2002. ACM Press.
12. D. B. Thomas and W. Luk. High quality uniform random number generation through lut optimised linear recurrences. In Proc. International Conference on Field-Programmable Technology. IEEE Computer Society, 2005.
13. D. B. Thomas and W. Luk. Efficient hardware generation of random variates with arbitrary distributions. In Proc. IEEE Symposium on FPGAs for Custom Computing Machines, 2006.
14. D. B. Thomas and W. Luk. Non-uniform random number generation through piecewise linear approximations. In Proc. International Conference on Field Programmable Logic and Applications, 2006.
15. Virtex-4 - Why are the FIFO16 flags not working correctly? Technical Report AR22462, Xilinx Inc., 2006.
16. Xilinx, Inc. Virtex-II Platform FPGAs: Complete Data Sheet, 2000.
17. Xilinx, Inc. XtremeDSP for Virtex-4 FPGAs User Guide, 2005.
18. L. Zhuo and V. K. Prasanna. Sparse matrix-vector multiplication on FPGAs. In Proc. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 63-74. ACM Press, 2005.