VLSI design of multi standard turbo decoder for 3G and beyond

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2007, Pages 589-594

  Ahmed, Imran ^a   Arslan, Tughrul ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CODES (STANDARDS); CODES (SYMBOLS); COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; DYNAMIC MODELS; ELECTRIC POWER TRANSMISSION; INDUSTRIAL ENGINEERING; MECHANIZATION; METROPOLITAN AREA NETWORKS; NETWORK ARCHITECTURE; STANDARDS; TRANSMISSIONS; TURBO CODES; VITERBI ALGORITHM;

ACCESS TECHNOLOGIES; CDMA 2000; CLOCK CYCLES; COMPUTATION KERNEL; CONTEXT SWITCHING; DESIGN AUTOMATION CONFERENCE (DAC); DYNAMIC RECONFIGURATIONS; EXCELLENT PERFORMANCE; IEEE 802.16; MULTI-STANDARD; PROCESS TECHNOLOGIES; RE-CONFIGURABLE; SOUTH PACIFIC; SYSTEM ON CHIP (SOCS); TRANSMISSION SYSTEMS; TURBO (ITERATIVE) DECODING; TURBO DECODERS; VITERBI; VITERBI DECODER (VD); VLSI DESIGNS;

DECODING;

EID: 46649104956     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2007.358050     Document Type: Conference Paper

References (14)

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