A retargetable software timing analyzer using architecture description language

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2007, Pages 396-401

  Li, Xianfeng ^a   Roychoudhury, Abhik ^b   Mitra, Tulika ^b   Mishra, Prabhat ^c   Cheng, Xu ^a  

^a PEKING UNIVERSITY   (China)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c J Crayton Pruitt Family Department of Biomedical Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; EMBEDDED SYSTEMS; INDUSTRIAL ENGINEERING; LARGE SCALE SYSTEMS; LEAD; LINGUISTICS; MECHANIZATION; MULTIPROCESSING SYSTEMS; PIPELINES; PROGRAM PROCESSORS; REAL TIME SYSTEMS; REGRESSION ANALYSIS; STATIC ANALYSIS; SYSTEMS ANALYSIS; TIME MEASUREMENT;

ARCHITECTURE DESCRIPTION LANGUAGE (ADL); BRANCH PREDICTION; DESIGN AUTOMATION CONFERENCE (DAC); EMBEDDED PROCESSORS; EXECUTION MODELS; GRAPH-BASED; MICROARCHITECTURE MODELING; MODERN PROCESSORS; PARAMETERIZED MODELING; PATH ANALYSIS; PIPELINE MODELING; REAL-TIME SYSTEMS; RETARGETABILITY; RETARGETABLE; SCHEDULABILITY ANALYSIS; SOUTH PACIFIC; STATIC WCET ANALYSIS; WCET ANALYSIS; WORST-CASE EXECUTION TIME (WCET);

PIPELINE PROCESSING SYSTEMS;

EID: 46649098218     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2007.358018     Document Type: Conference Paper

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