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Volumn , Issue , 2007, Pages 601-608

Improving XOR-dominated circuits by exploiting dependencies between operands

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATION; CARRY LOGIC; CODES (SYMBOLS); COMPLEXATION; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; DIGITAL ARITHMETIC; DIGITAL INTEGRATED CIRCUITS; FREQUENCY MULTIPLYING CIRCUITS; FUZZY LOGIC; INDUSTRIAL ENGINEERING; LOGIC DESIGN; MECHANIZATION; MULTIPLYING CIRCUITS; NETWORKS (CIRCUITS); SHAPE OPTIMIZATION; STANDARDS; STRUCTURAL OPTIMIZATION;

EID: 46649092954     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2007.358052     Document Type: Conference Paper
Times cited : (12)

References (19)
  • 4
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    • R. E. Bryant. The complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication. IEEE Transactions on Computers, 40(2):205-13, Feb. 1991.
    • (1991) IEEE Transactions on Computers , vol.40 , Issue.2 , pp. 205-213
    • Bryant, R.E.1
  • 7
    • 85176694586 scopus 로고    scopus 로고
    • C. Lee, M. Potkonjak, and W. H. Mangione-Smith. MediaBench: A tool for evaluating and synthesizing multimedia and communicatons systems. In Proceedings of the 30th Annual International Symposium on Microarchitecture, pages 330-35, Research Triangle Park, N.C., Dec. 1997.
    • C. Lee, M. Potkonjak, and W. H. Mangione-Smith. MediaBench: A tool for evaluating and synthesizing multimedia and communicatons systems. In Proceedings of the 30th Annual International Symposium on Microarchitecture, pages 330-35, Research Triangle Park, N.C., Dec. 1997.
  • 9
    • 17644373718 scopus 로고    scopus 로고
    • A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach
    • Mar
    • V. G. Oklobdzija, D. Villeger, and S. S. Liu. A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach. IEEE Transactions on Computers, C-45(3):294-306, Mar. 1996.
    • (1996) IEEE Transactions on Computers , vol.C-45 , Issue.3 , pp. 294-306
    • Oklobdzija, V.G.1    Villeger, D.2    Liu, S.S.3
  • 13
    • 0026218953 scopus 로고
    • Circuit and architecture trade-offs for high speed multiplication
    • Sept
    • P. Song and G. De Micheli. Circuit and architecture trade-offs for high speed multiplication. IEEE Journal of Solid-State Circuits, 26(9), Sept. 1991.
    • (1991) IEEE Journal of Solid-State Circuits , vol.26 , Issue.9
    • Song, P.1    De Micheli, G.2
  • 15
    • 46649083408 scopus 로고    scopus 로고
    • Synopsys. Creating High-Speed Data-Path Components, Application Note, Aug. 2001. Version 2001.08
    • Synopsys. Creating High-Speed Data-Path Components - Application Note, Aug. 2001. Version 2001.08.
  • 16
    • 0035272390 scopus 로고    scopus 로고
    • An optimal allocation of carry-save-adders in arithmetic circuits
    • Mar
    • J. Um and T. Kim. An optimal allocation of carry-save-adders in arithmetic circuits. IEEE Transactions on Computers, C-50(3):215-33, Mar. 2001.
    • (2001) IEEE Transactions on Computers , vol.C-50 , Issue.3 , pp. 215-233
    • Um, J.1    Kim, T.2
  • 17
    • 16244396717 scopus 로고    scopus 로고
    • Improved use of the carry-save representation for the synthesis of complex arithmetic circuits
    • San Jose, Calif, Nov
    • A. K. Verma and P. Ienne. Improved use of the carry-save representation for the synthesis of complex arithmetic circuits. In Proceedings of the International Conference on Computer Aided Design, pages 791-98, San Jose, Calif., Nov. 2004.
    • (2004) Proceedings of the International Conference on Computer Aided Design , pp. 791-798
    • Verma, A.K.1    Ienne, P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.