Directed micro-architectural test generation for an industrial processor: A case study

Proceedings - International Workshop on Microprocessor Test and Verification

Volumn , Issue , 2006, Pages 33-36

  Koo, Heon Mo ^a   Mishra, Prabhat ^a   Bhadra, Jayanta ^b   Abadir, Magdy ^b  

^a J Crayton Pruitt Family Department of Biomedical Engineering   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE; MODEL CHECKING; PROGRAM PROCESSORS; SOFTWARE TESTING; SPECIFICATION LANGUAGES;

ARCHITECTURAL ARTIFACTS; ARCHITECTURAL LEVELS; AUTOMATED TECHNIQUES; FUNCTIONAL VALIDATION; INSTRUCTION SET ARCHITECTURE; SIMULATION-BASED VALIDATION; TEMPORAL LOGIC PROPERTIES; TEMPORAL SPECIFICATION;

COMPUTER ARCHITECTURE;

EID: 46449129684     PISSN: 15504093     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MTV.2006.10     Document Type: Conference Paper

References (14)

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