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Volumn II, Issue , 2005, Pages 736-741

Flexible hardware/software support for message passing on a distributed shared memory architecture

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SOFTWARE; EMBEDDED SYSTEMS; MULTIMEDIA SYSTEMS; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS; SYNCHRONIZATION;

EID: 33646950282     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.156     Document Type: Conference Paper
Times cited : (27)

References (13)
  • 2
    • 0029394470 scopus 로고
    • Overview of the PARADIGM compiler for distributed memory message-passing multicomputers
    • Mar.
    • P. Banerjee, J. Chandy, M. Gupta, J. Holm, A. Lain, D. Palermo, S. Ramaswamy, and E. Su. Overview of the PARADIGM Compiler for Distributed Memory Message-Passing Multicomputers. IEEE Computer, 28(10):37-37, Mar. 1995.
    • (1995) IEEE Computer , vol.28 , Issue.10 , pp. 37-37
    • Banerjee, P.1    Chandy, J.2    Gupta, M.3    Holm, J.4    Lain, A.5    Palermo, D.6    Ramaswamy, S.7    Su, E.8
  • 3
    • 0033097556 scopus 로고    scopus 로고
    • Producer-consumer communication in distributed shared memory multiprocessors
    • Mar.
    • G. Byrd and M. Flynn. Producer-Consumer Communication in Distributed Shared Memory Multiprocessors. Proc. IEEE, 87(3):456-166, Mar. 1999.
    • (1999) Proc. IEEE , vol.87 , Issue.3 , pp. 456-1166
    • Byrd, G.1    Flynn, M.2
  • 5
    • 33646926298 scopus 로고    scopus 로고
    • A 160mW, 80nA standby, MPEG-4 audiovisual LSI 16Mb embedded DRAM and a 5 GOPS adaptive post filter
    • H. A. et al. A 160mW, 80nA Standby, MPEG-4 Audiovisual LSI 16Mb Embedded DRAM and a 5 GOPS Adaptive Post Filter. In IEEE int. solid-state circuits conference, pages 62-63, 2003.
    • (2003) IEEE Int. Solid-state Circuits Conference , pp. 62-63
    • A., H.1
  • 6
    • 33646899464 scopus 로고    scopus 로고
    • Communication centric architectures for turbo-decoding on embedded multiprocessors
    • F.Gilbert, M. Thul, and N. When. Communication centric architectures for turbo-decoding on embedded multiprocessors. In Proc. Date, pages 10356-2003.
    • Proc. Date , pp. 10356-12003
    • Gilbert, F.1    Thul, M.2    When, N.3
  • 8
    • 4444343175 scopus 로고    scopus 로고
    • An efficient scalable and flexible data transfer architectures for multiprocessor SoC with massive distributed memory
    • S. Hand, A. Baghdadi, M. Bonacio, S. Chae, and A. Jerraya. An efficient scalable and flexible data transfer architectures for multiprocessor SoC with massive distributed memory. In Proc. 41 Dac, pages 250-255, 2004.
    • (2004) Proc. 41 Dac , pp. 250-255
    • Hand, S.1    Baghdadi, A.2    Bonacio, M.3    Chae, S.4    Jerraya, A.5
  • 10


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.