TTL hardware interface: A high-level interface for streaming multiprocessor architectures

Proceedings of the 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia, ESTIMEDIA 2006

Volumn , Issue , 2006, Pages 107-112

  Henriksson, Tomas ^a   Van Der Wolf, Pieter ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

BIOLOGICAL MATERIALS; COMPUTER PROGRAMMING LANGUAGES; DIGITAL ARITHMETIC; DIGITAL COMMUNICATION SYSTEMS; DISTRIBUTED COMPUTER SYSTEMS; ELECTRIC NETWORK TOPOLOGY; EMBEDDED SYSTEMS; INTEGRATED CIRCUITS; MISSILE LAUNCHING SYSTEMS; MULTIMEDIA SYSTEMS; NETWORK ARCHITECTURE; REAL TIME SYSTEMS; SYSTEMS ANALYSIS;

ADDRESS GENERATION; CASE STUDIES; CO-PROCESSORS; DIGITAL CHIPS; HARDWARE INTERFACES; HIGH PERFORMANCE; LOW-POWER CONSUMPTION; MESSAGE PASSING INTERFACE (MPI); MESSAGE PASSING INTERFACES (MPI); MULTI-PROCESSOR ARCHITECTURES; MULTIMEDIA APPLICATIONS; NETWORK INTERFACES; NETWORKS ON CHIPS (NOCS); REAL-TIME MULTIMEDIA; SPECIFIC HARDWARE; STREAMING DATA; TASK TRANSACTION LEVELS;

MESSAGE PASSING;

EID: 46249110062     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESTMED.2006.321282     Document Type: Conference Paper

References (14)

1. P. Martin. A comparison of Network on-Chip and Busses. At http://www.chipdesignmag.com/display.php?articleId=371
2. A. Radulescu et al. An Efficient On-Chip NI Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration. In IEEE Trans. on Computer-aided Design of Integrated Circuits and Ssystems, pages 4-17, vol. 24, no. 1, January 2005.
3. M. Millberg et al. The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip. In Proceedings of the 17th International Conference on VLSI Design, pages 693-696, 2004.
4. E. de Kock et al. YAPI: Application Modelling for Signal Processing Systems. In Proc. of 37th Design Automation Conference, pages 402-405, June 2000.
5. A. Burchard et al. A Real-Time Streaming Memory Controller. In Proceedings of Design Automation and Test in Europe Designers' Forum, pages 20-25, March 2005.
6. J.A. Rowson, A. Sangiovanni-Vincentelli. Interface-Based Design. In Proceedings of 34th Design Automation Conference, pages 178-183, June 1997.
7. W.O. Cesario et al. Multiprocessor SoC platforms: a component-based design approach. In IEEE Design & Test of Computers, pages 52-63, vol. 19, issue 6, Nov.-Dec. 2002.
8. M. Bekooij et al. Dataflow Analysis for Real-time Embedded Multiprocessor System Design. In Dynamic and Robust Streaming in and between Connected Consumer-electronic Devices (P. van der Stok, Ed.), pages 81-108. Springer, 2005.
9. C. Bergen, J. Lynch. Streaming Interface (NPSI) Implementation Agreement. At http://www.npforum.org/techinfo/HWStreamingIA.pdf
10. A. Nieuwland et al. C-HEAP: A Heterogeneous Multi-processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems. In Kluwer Journal of Design Automation for Embedded Systems, vol. 7, no. 3, pp. 233-270, ISSN 0929-5585, October 2002.
11. P. van der Wolf et al. Design and Programming of Embedded Multiprocessors: An Interface-Centric Approach. In ISSS+CODES 2004 Conference Proceedings, pages 206-217, ISSS+CODES, September 2004.
12. M. Rutten et al. A Heterogeneous Multiprocessor Architecture for Flexible Media Processing. IEEE Design & Test of Computers, pages 39-50, vol. 19, issue 4, Jul.-Aug. 2002.
13. OCP Specification. At http://www.ocpip.org/
14. ARM AMBA 3 AXI Specification. At http://www.arm.com/