On-line test vector generation from temporal constraints written in PSL

IFIP VLSI-SoIC 2006 - IFIP WG 10.5 International Conference on Very Large Scale Integration and System-on-Chip

Volumn , Issue , 2006, Pages 397-402

  Oddos, Yann ^a   Morin Allory, Katell ^a   Borrione, Dominique ^a  

^a TIMA LABORATORY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BOOLEAN FUNCTIONS; INTEGRATED CIRCUITS; LSI CIRCUITS; PROGRAMMABLE LOGIC CONTROLLERS; SPACE PLATFORMS; TESTING;

DEVICE-UNDER-TEST (DUT); EFFICIENT SOLUTIONS; INTERNATIONAL CONFERENCES; LINE TESTING; PROPERTY (S); SYSTEM ON CHIP (SOCS); TEMPORAL CONSTRAINTS; TEST VECTORS; VECTOR GENERATION; VERY LARGE SCALE INTEGRATION (VLSI);

VECTORS;

EID: 46249088375     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISOC.2006.313221     Document Type: Conference Paper

References (9)

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