System level synthesis of multiple ip blocks in the behavioral synthesis tool

Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems

Volumn 15, Issue 1, 2003, Pages 363-368

  Mukherjee, Rajarshi ^a   Jones, Alex ^a   Banerjee, Prith ^a  

^a Northwestern University   (United States)

Author keywords

C C++; IP; RTL VHDL; SOC; System Level Synthesis

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; C (PROGRAMMING LANGUAGE); COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; FIELD PROGRAMMABLE GATE ARRAYS; FIR FILTERS; INTERFACES (COMPUTER); LARGE SCALE SYSTEMS; MULTIPLEXING; PROGRAM COMPILERS; RANDOM ACCESS STORAGE;

C/C++; IP; REGISTER TRANSFER LEVEL (RTL); SOC; SYSTEM-LEVEL SYNTHESIS; VHDL;

INTEGRATED CIRCUITS;

EID: 1542642701     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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