Full wafer integration of NEMS on CMOS by nanostencil lithography

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2006, Pages

  Arcamone, Julien ^a   Van Den Boogaart, Marc A F ^b   Serra Graells, Francesc ^a   Hansen, Sven ^c   Brugger, Jürgen ^b   Torres, Francesc ^d   Abadal, Gabriel ^d   Barniol, Núria ^d   Pérez Murano, Francesc ^a  

^a INSTITUTO DE MICROELECTRÓNICA DE BARCELONA   (Spain)

^b EPFL   (Switzerland)

^c SUSS MicroTec Lithography GmbH   (United States)

^d UNIVERSITAT AUTÒNOMA DE BARCELONA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRON DEVICES; LITHOGRAPHY; METALS; MONOLITHIC INTEGRATED CIRCUITS; NONMETALS; RESONANCE; SILICON; STANDARDS;

CMOS CIRCUITS; DC VOLTAGES; METAL EVAPORATION; MONOLITHICALLY INTEGRATED; NANO-DEVICES; NANOSTENCIL LITHOGRAPHY; PATTERN TRANSFERRING; POST-PROCESSING; RESONANCE FREQUENCIES; SACRIFICIAL LAYERS; SILICON CANTILEVERS; STANDARD CMOS; WAFER-SCALE;

SILICON WAFERS;

EID: 46049106792     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2006.346830     Document Type: Conference Paper

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