Solving the gate ACLV and ADLV challenges with printing assist features

Microlithography World

Volumn 17, Issue 2, 2008, Pages 7-10

  Haffner, Henning ^a   Meiring, Jason ^b   Baum, Zachary ^c   Halle, Scott ^c   Mansfield, Scott ^c  

^a INFINEON TECHNOLOGIES   (United States)

^b IBM   (United States)

^c IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASSIST FEATURES; AUTOMATICALLY GENERATED; DECOMPOSITION APPROACH; DOUBLE PATTERNING; GATE LEVELS; LINE ENDS; LINE WIDTH VARIATION; SINGLE EXPOSURE;

PRINTING;

EID: 45549090899     PISSN: 1074407X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (4)

1. Yan Borodovsky, "Marching to the Beat of Moore's Law," Proc. SPIE, Vol. 6153 (SPIE, Bellingham, WA, 2006) 615301.
2. H. Zhuang, H. Wang, C. Yap, A. Gutmann, J. Lian, C. Sarma et al., "Patterning Strategies for Gate-Level Tip-tip Distance Reduction in SRAM cells for 45nm and Beyond," Semiconductor Technology, ISTC 2007, Proc. Vol. 2007-01, 154-159, 2007.
3. J. Meiring, H. Haffner, C. Fonseca, S. Halle, S. Mansfield: "ACLV Driven Double-Patterning Decomposition With Extensively Added Printing Assist Features (PrAFs)," Proc. SPIE, Vol. 6520 (SPIE, Bellingham, WA, 2007) 65201U.
4. H. Haffner, J. Meiring, Z. Baum, S. Halle, "Paving the Way to a Full-chip Gate-level Double Patterning Application." Proc. SPIE, Vol. 6730 (SPIE, Bellingham, WA, 2007) 67302C.