Two-dimensional folding strategies for improved layouts of cyclic shifters

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

Volumn , Issue , 2004, Pages 277-278

  Seidel, Peter Michael ^a   Fazel, Kenneth ^a  

^a Southern Methodist University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BASIC GATES; CONSTRAINTS; CYCLIC SHIFTERS; LAYOUTS;

ENERGY UTILIZATION; GATES (TRANSISTOR); LOGIC GATES; OPTIMIZATION; PROBLEM SOLVING; ROUTERS;

LOGIC CIRCUITS;

EID: 4544362539     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2004.1339556     Document Type: Conference Paper

References (5)

1. K.P. Acken, M.J. Irwin, and R.M. Owens. Power comparisons for barrel shifters. In Low Power Electronics and Design, International Symposium on, pages 209-212. IEEE Society Press, 1996.
2. P.W. Bosshart and Q.D. An. Shifter circuit for an arithmetic logic unit in a microprocessor. U.S. patent 5896305, 1999.
3. W.J. Paul and P.-M. Seidel. To Booth or Not To Booth? INTEGRATION, the VLSI journal, 23:5-40, 2002.
4. P.-M. Seidel, M. Hillebrand, and T. Schuerger. Reducing Wire Lengths in the Layout of Cyclic Shifters. IEICE Transactions, Special Section on VLSI and CAD Algorithms, E84-A(11):2714-2721, 2001.
5. L. Sigal et al. Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor. IBM Journal of Research and Development, 41(4/5):489-502, 1997.