Reducing wire lengths in the layout of cyclic shifters

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E84-A, Issue 11, 2001, Pages 2714-2721

  Seidel, Peter Michael ^a   Hillebrand, Mark A ^b   Schurger, Thomas ^b  

^a SOUTHERN METHODIST UNIVERSITY   (United States)

^b SAARLAND UNIVERSITY   (Germany)

Author keywords

Cyclic shifter; Layout; Wire delay; Wire length

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER SIMULATION; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; LOGIC GATES; MICROPROCESSOR CHIPS; OPTIMIZATION; SHIFT REGISTERS;

CYCLIC SHIFTERS; POWER DISSIPATION; WIRE DELAY; WIRE LENGTHS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035518180     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (11)

1. Power comparisons for barrel shifters
2. Shifter circuit for an arithmetic logic unit in a microprocessor
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7. Circuit design techniques for the high-performance CMOS IM S/390 parallel enterprise server G4 microprocessor