To booth or not to booth

Integration, the VLSI Journal

Volumn 32, Issue 1-2, 2002, Pages 5-40

  Paul, Wolfgang J ^a   Seidel, Peter Michael ^b  

^a SAARLAND UNIVERSITY   (Germany)

^b Southern Methodist University   (United States)

Author keywords

Booth recoding; Delay and area complexity; Layout analysis; Multiplier design; VLSI model; Wire effects

Indexed keywords

ADDERS; MATHEMATICAL MODELS; MULTIPLYING CIRCUITS; THEOREM PROVING; TREES (MATHEMATICS);

BINARY MULTIPLICATION; BOOTH RECODING;

VLSI CIRCUITS;

EID: 0036857592     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9260(02)00040-8     Document Type: Article

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