Investigation of Ni fully silicided gates for sub-45 nm CMOS technologies

Microelectronic Engineering

Volumn 76, Issue 1-4, 2004, Pages 349-353

  Pawlak, M A ^a,b   Kittl, J A ^c   Chamirian, O ^a,b   Veloso, A ^b   Lauwers, A ^b   Schram, T ^b   Maex, K ^b   Vantomme, A ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

^b IMEC   (Belgium)

^c TEXAS INSTRUMENTS   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CALIBRATION; CAPACITORS; CMOS INTEGRATED CIRCUITS; DEGRADATION; DIELECTRIC MATERIALS; DOPING (ADDITIVES); ELECTRIC RESISTANCE; NICKEL COMPOUNDS; PARAMETER ESTIMATION; REACTION KINETICS; THERMODYNAMIC STABILITY;

CMOS TECHNOLOGY; MID-GAP MATERIALS; POLY-DEPLETION; SILICIDATION;

GATES (TRANSISTOR);

EID: 4544328850     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2004.07.037     Document Type: Conference Paper

References (6)

1. ITRS roadmap, 2001. Available from: http://public.itrs.net/.
2. I. De, D. Johri, A. Srivastava, C.M. Osburn, Impact of gate work function on device performance at the 50 nm technology node, Solid-State Electron. 44 (2000) 1077.
3. I. Polischuk, P. Ranade, T.J. King, C. Hu, Dual work function metal gate CMOS transistors by Ni-Ti interdifiusion, IEEE Electron Device Lett. 23 (2002) 200.
4. Q. Lu, R. Lin, P. Randae, T.J. King, C. Hu, Metal gate work function adjustment for future CMOS technology, Symp. VLSI Tech. Dig. (2001).
5. 2 polysilicon: a novel approach to very low-resistive gate (∼2Ω/) without metal CMP nor etching, IEDM Tech. Dig. (2001).
6. W.P. Maszara, Z. Krivokapic, P. King, J.S. Gollgweon, M.R. Lin, Transistors with dual work function metal gate by single full silicidation (FUSI) of polysilicon gates, IEDM Tech. Dig. (2002).