Electromagnetic modelling of switching noise in on-chip power distribution networks

Proceedings of the International Conference on Electromagnetic Interference and Compatibility

Volumn 2003-January, Issue , 2003, Pages 47-52

  Mao, Jifeng ^a   Kim, Woopoung ^a   Choi, Suna ^a   Swaminathan, M ^a   Libous, J ^b   O'connor, D ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b IBM   (United States)

Author keywords

Circuit noise; Circuit simulation; Dielectric losses; Dielectric substrates; Electromagnetic interference; Electromagnetic modeling; Finite difference methods; Network on a chip; Power systems; Rails

Indexed keywords

CIRCUIT SIMULATION; COMPUTATIONAL ELECTROMAGNETICS; DIELECTRIC DEVICES; DIELECTRIC LOSSES; ELECTRIC NETWORK ANALYSIS; ELECTROMAGNETIC PULSE; ELECTROMAGNETIC WAVE INTERFERENCE; FINITE DIFFERENCE METHOD; FINITE DIFFERENCE TIME DOMAIN METHOD; RAILS; SANITARY SEWERS; SIGNAL INTERFERENCE; STANDBY POWER SYSTEMS; SUBSTRATES; SWITCHING; TIME DOMAIN ANALYSIS;

CIRCUIT NOISE; DIELECTRIC SUBSTRATES; ELECTROMAGNETIC MODELING; ELECTROMAGNETIC MODELLING; FINITE DIFFERENCE TIME DOMAIN TECHNIQUE; NETWORK ON A CHIP; ON-CHIP POWER DISTRIBUTION; SIMULTANEOUS SWITCHING NOISE;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 4544276928     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICEMIC.2003.237781     Document Type: Conference Paper

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