Operating systems in silicon and the dynamic management of resources in many-core chips

Parallel Processing Letters

Volumn 18, Issue 2, 2008, Pages 257-274

  Jesshope, Chris ^a  

^a UNIVERSITY OF AMSTERDAM   (Netherlands)

Author keywords

Dynamic resource management; Multi cores; Operating systems; SVP concurrency model

Indexed keywords

CONCURRENCY CONTROL; JOB SATISFACTION; NETWORK MANAGEMENT; PROBLEM SOLVING; PROGRAM PROCESSORS; RESOURCE ALLOCATION;

CONCURRENCY MODEL; DYNAMIC RESOURCE MANAGEMENT; JOB SCHEDULING;

COMPUTER OPERATING SYSTEMS;

EID: 44649191685     PISSN: 01296264     EISSN: None     Source Type: Journal    
DOI: 10.1142/S0129626408003375     Document Type: Article

References (26)

1. Krste Asanovic, et. al. (2006) The Landscape of Parallel Computing Research: A View from Berkeley, Technical Report No. UCBEECS-2006-183.
2. D May and R Shepherd (1984) The transputer implementation of occam, Proc. Intl Conf on Fifth-Generation Computer Systems, Tokyo, pp533-541.
3. E lee (2006) The problem with threads, IEEE Computer, 36(5), pp. 33-42.
4. A Bolychevsky, C R Jesshope and V B Muchnick, (1996) Dynamic scheduling in RISC architectures, IEE Trans. E, Computers and Digital Techniques, 143, pp 309-317.
5. C R Jesshope (1992) The f-code abstract machine and its implementation, Proc COMPEURO 92 (IEEE Press) pp 169-174.
6. V B Muchnick and A B Shafarenko (1996) Data Parallel Computing - the Language Dimension, ISBN: 1 85032 179 5, Chapman Hall.
7. Jesshope C. R. (2006) Microthreading a model for distributed instruction-level concurrency, Parallel processing Letters, 16(2), pp209-228, ISSN: 0129-6264.
8. R. Allen and K. Kennedy (2001) Optimizing Compilers for Modern Architectures. Morgan Kaufmann Publishers, ISBN 1-55860-286-0.
9. H Kasahara, M Obata, K Ishizaka, K Kimura, H Kaminaga, H Nakano, K Nagasawa, A Murai, H Itagaki, and J Shirako (2002) Multigrain automatic parallelization in Japanese millennium project IT21 advanced parallelizing compiler, PARELEC 02: Proc. of the Intl. Conf. Parallel Computing in Electrical Engineering (Washington, DC, USA), IEEE Computer Society, p. 105.
10. J W Moore (1983) The HEP Parallel Processor, Los Alamos Science, Fall 1983, pp 72-75.
11. Alverson, R. et al. (1990) The Tera Computer System, Proc. of the 4th International Conference on Supercomputing, Amsterdam, The Netherlands, 11-15 June, pp. 1-6. ACM Press, New York, NY, USA.
12. J W Berry, B A Hendrickson, S Kalian and P Konecny (2006) Graph Software Development and Performance on the MTA-2 and Eldorado, 48th Cray Users Group Meeting, Switzerland, May 2006.
13. G M Papadopoulos and D E Culler (1990) Monsoon: An Explicit Token Store Architecture, Proc. 17th International Symposium on Computer Architecture, pp82-91
14. G M Papadopoulos and D E Culler (1998) Retrospective: Monsoon: An Explicit Token Store Architecture, In 25 Years of the International Symposia on Computer Architecture: Selected Papers, pp. 7476.
15. A. E. Eichenberger, et. al. (2005) Optimizing Compiler for the CELL Processor, Proc 14th Intl. Conf. on Parallel Architectures and Compilation Techniques (PACT), pp 161172, Washington, DC, USA, 2005. IEEE Computer Society.
16. Richard A. Hankins, Gautham N. Chinya, Jamison D. Collins, Perry H. Wang, Ryan Rakvic, Hong Wang, John P. Shen (2006) Multiple Instruction Stream Processor, Proc 33rd International Symposium on Computer Architecture (ISCA'O6), pp. 114-127.
17. R Nikhil Arvind and K Pingali (1989) I-Structures: Data structures for parallel computing (1989) ACM Transactions on Programming Languages and Systems, 11.
18. T.D Vu and C. R. Jesshope (2007) Formalizing SANE virtual processor in thread algebra, in M. Butler, M. G. Hinchley and M. M. Larrondo-Petrie, eds. ICFEM 2007, pp 345-365.
19. H L Muller, P W A Stallard, D H D Warren (1995) Hiding Miss Latencies with Multithreading on the Data Diffusion Machine, Proc. 1995 Intl. Conf. on Parallel Processing, ICPP 95, Volume I, ISBN 0-8493-2615-X, pp178-185.
20. G R Gao and V Sarkar (2000) Location consistency-a new memory model and cache consistency protocol Computers, IEEE Trans. Comput. 49 (8), pp798-813.
21. M. W. van Tol, C. R. Jesshope, M. Lankamp and S. Polstra (2008) An implementation of the SANE Virtual Processor using POSIX threads, submitted to Journal of Systems Architecture.
22. Jesshope, C R (2006) μTC-an intermediate language for programming chip multiprocessors, Proc. Pacific Computer Systems Architecture Conference 2006 - ACSACO6, ISBN 3-540-4005, LNCS 4186, pp147-160.
23. G Heiser (1998) The Mungi Single-Adress-Space Operating System, Software: Practice and Experience, 28(9), pp.901-928.
24. J S Chase et. al. (1994) Sharing and Protection in a Single-Address-Space Operating System, ACM TOCS, 12,(4), pp.271-307.
25. A C Skousen and D S Miller (1998) Operating System Structure and Processor Architecture for a Large Distributed Single Address Space, Proceedings of PDCS 98: 10th International Conference on Parallel and Distributed Computing Systems, pp 631-634.
26. R Fabry (1974) Capability-based addressing, CACM, 7 no 7, pp 403-412.