Multigrain automatic parallelization in Japanese Millennium Project IT21 Advanced Parallelizing Compiler

Proceedings - International Conference on Parallel Computing in Electrical Engineering, PARELEC 2002

Volumn , Issue , 2002, Pages 105-111

  Kasahara, H ^a   Obata, M ^a   Ishizaka, K ^a   Kimura, K ^a   Kaminaga, H ^a   Nakano, H ^a   Nagasawa, K ^a   Murai, A ^a   Itagaki, H ^a   Shirako, J ^a  

^a WASEDA UNIVERSITY   (Japan)

Author keywords

Algorithms; Data analysis; Government; Memory architecture; Multiprocessing systems; Parallel processing; Program processors; Testing; Usability; Workstations

Indexed keywords

ALGORITHMS; CACHE MEMORY; COMPUTER WORKSTATIONS; DATA REDUCTION; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS; MULTIPROCESSING PROGRAMS; MULTIPROCESSING SYSTEMS; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS; SHAPE MEMORY EFFECT; SOFTWARE TESTING; TESTING;

AUTOMATIC PARALLELIZATION; CHIP MULTIPROCESSOR; CURRENT PERFORMANCE; FINE GRAIN PARALLELISM; GOVERNMENT; PARALLEL PROCESSING; PARALLELIZING COMPILER; USABILITY;

PROGRAM COMPILERS;

EID: 44649120286     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PCEE.2002.1115213     Document Type: Conference Paper

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