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Volumn 52, Issue 8, 2004, Pages 1242-1247

Selective avoidance of cycles in irregular LDPC code construction

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BIT ERROR RATE; BLOCK CODES; COMPUTER SIMULATION; DECODING; GRAPH THEORY; ITERATIVE METHODS; SET THEORY; THEOREM PROVING;

EID: 4444318644     PISSN: 00906778     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCOMM.2004.833048     Document Type: Article
Times cited : (313)

References (13)
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  • 4
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  • 5
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    • Bit vs. Symbol interleaving for parallel concatenated trellis-coded modulation
    • San Antonio, TX, Nov
    • C. Fragouli and R. D. Wesel, "Bit vs. symbol interleaving for parallel concatenated trellis-coded modulation," in Proc. IEEE Global Telecommunications Conf., vol. 2, San Antonio, TX, Nov. 2001, pp. 931-935.
    • (2001) Proc. IEEE Global Telecommunications Conf. , vol.2 , pp. 931-935
    • Fragouli, C.1    Wesel, R.D.2
  • 6
    • 0033337059 scopus 로고    scopus 로고
    • Comparison of constructions of irregular Gallager codes
    • Oct
    • D. J. C. MacKay, S. T. Wilson, and M. C. Davey, "Comparison of constructions of irregular Gallager codes," IEEE Trans. Commun., vol. 47, pp. 1449-1454, Oct. 1999.
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  • 7
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    • Good error-correcting codes based on very sparse matrices
    • Mar
    • D. J. C. MacKay, "Good error-correcting codes based on very sparse matrices," IEEE Trans. Inform. Theory, vol. 45, pp. 399-431, Mar. 1999.
    • (1999) IEEE Trans. Inform. Theory , vol.45 , pp. 399-431
    • MacKay, D.J.C.1
  • 8
    • 0035246127 scopus 로고    scopus 로고
    • Design of capacity-approaching irregular low-density parity-check codes
    • Feb
    • T. Richardson, M. Shokrollahi, and R. Urbanke, "Design of capacity-approaching irregular low-density parity-check codes," IEEE Trans. Inform. Theory, vol. 47, pp. 638-656, Feb. 2001.
    • (2001) IEEE Trans. Inform. Theory , vol.47 , pp. 638-656
    • Richardson, T.1    Shokrollahi, M.2    Urbanke, R.3
  • 9
    • 0034865418 scopus 로고    scopus 로고
    • A heuristic search for good low-density parity-check codes at short block lengths
    • Helsinki, Finland, June
    • Y. Mao and A. H. Banihashemi, "A heuristic search for good low-density parity-check codes at short block lengths," in Proc. IEEE Int. Conf. Communications, vol. 1, Helsinki, Finland, June 2001, pp. 41-44.
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    • Mao, Y.1    Banihashemi, A.H.2
  • 11
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    • Finite length analysis of low-density parity-check codes on the binary erasure channel
    • June
    • C. Di, D. Proietti, E. Telatar, T. Richardson, and R. Urbanke, "Finite length analysis of low-density parity-check codes on the binary erasure channel," IEEE Trans. Inform. Theory, vol. 48, pp. 1570-1579, June 2002.
    • (2002) IEEE Trans. Inform. Theory , vol.48 , pp. 1570-1579
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  • 12
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  • 13
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    • Lowering the error-rate floors of moderate-length high-rate irregular LDPC codes
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    • M. Yang and W. E. Ryan, "Lowering the error-rate floors of moderate-length high-rate irregular LDPC codes," in IEEE Int. Symp. Information Theory, Yokohama, Japan, June 2003, p. 237.
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    • Yang, M.1    Ryan, W.E.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.