The CBP parameter: A module characterization approach for DSP software optimization

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 38, Issue 2, 2004, Pages 131-146

  Bhattacharyya, Shuvra S ^a   Murthy, Praveen K ^b  

^a UNIVERSITY OF MARYLAND   (United States)

^b FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

Array lifetime; Block diagram compilers; Buffer overlaying; Dataflow; Design methodology; Embedded systems; Graph coloring; Lifetime analysis

Indexed keywords

ARRAY LIFETIME; BLOCK DIAGRAM COMPLIERS; DATAFLOW;

COMPUTER SOFTWARE; DATA STORAGE EQUIPMENT; DATA TRANSFER; GRAPH THEORY; OPTIMIZATION; PARAMETER ESTIMATION;

DIGITAL SIGNAL PROCESSING;

EID: 4444308652     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: 10.1023/B:VLSI.0000040425.26993.b4     Document Type: Review

References (38)

1. P.K. Murthy, E.G. Cohen, and S. Rowland, "System Canvas: A New Design Environment for Embedded DSP and Telecommunication Systems," in Proceedings of the International Workshop on Hardware/ Software Co-Design, April 2001.
2. S. Ritz, M. Pankert, and H. Meyr, "High Level Software Synthesis for Signal Processing Systems," in Proceedings of the International Conference on Application Specific Array Processors, Aug. 1992, pp. 679-693.
3. R. Lauwereins, M. Engels,J.A. Peperstraete, E. Steegmans, and J.V. Ginderdeuren, "GRAPE: A CASE Tool for Digital Signal Parallel Processing," IEEE ASSP Magazine, vol. 7, no. 2, 1990, pp. 32-43.
4. J. Buck, S. Ha, E.A. Lee, and D.G. Messerschmitt, "Ptolemy: A Framework for Simulating and Prototyping Heterogeneous Systems," International Journal of Computer Simulation, vol. 4, 1994, pp. 155-182.
5. S. Sriram and S.S. Bhattacharyya, Embedded Multiprocessors: Scheduling and Synchronization, Marcel Dekker, Inc., 2000.
6. V. Zivojnovic, J.M. Velarde, C. Schlager, and H. Meyr, "DSPStone - A DSP-Oriented Benchmarking Methodology," International Conference on Signal processing Applications and Technology, Oct. 1994, pp. 715-720.
7. P.K. Murthy and S.S. Bhattacharyya, "Shared Buffer Implementations of Signal Processing Systems using Lifetime Analysis Techniques," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 2, 2001, pp. 177-198.
8. G. Araujo and S. Malik, "Code Generation for Fixed-Point DSPs," ACM Transactions on Design Automation of Electronic Systems, vol. 3, no. 2, 1998, pp. 136-161.
9. S.S. Bhattacharyya, R. Leupers, and P. Marwedel, "Software Synthesis and Code Generation for DSP, "IEEE Transactions on Circuits and Systems - II: Analog and Digital Signal Processing, vol. 47, no. 9, 2000, pp. 849-875.
10. R. Leupers and P. Marwedel, "Retargetable Code Generation Based on Structural Processor Descriptions," Journal of Design Automation for Embedded Systems, vol. 3, no. 1, 1998, pp. 75-108.
11. S. Liao, S. Devadas, K. Keutzer, S. Tjiang, and A. Wang, "Code Optimization Techniques in Embedded DSP Microprocessors," Journal of Design Automation for Embedded Systems, vol. 3, no. 1, 1998, pp. 59-73.
12. P. Marwedel and G. Goossens (Eds.), Code Generation for Embedded Processors, Kluwer Academic Publishers, 1995.
13. A.K. Kulkarni, A. Dube, and B.L. Evans, "Benchmarking Code Generation Methodologies for Programmable Digital Signal Processors," Technical Report. Department of Electrical and Computer Engineering, University of Texas at Austin, 1997.
14. J.E. Hopcroft and J. D. Ullman, Introduction to Automata Theory, Languages, and Computation, Addison-Wesley, 1979.
15. P.K. Murthy and S.S. Bhattacharyya, "Systematic Consolidation of Input and Output Buffers in Synchronous Dataflow Specifications," in Proceedings of the IEEE Workshop on Signal Processing Systems, Lafayette, Louisiana, October 2000, pp. 673-682.
16. P.K. Murthy and S.S. Bhattacharyya, "Buffer Merging: A Powerful Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications," in Proceedings of the International Symposium, on System Synthesis, San Jose, California, Nov. 1999, pp. 78-84.
17. S.S. Bhattacharyya, P.K. Murthy, and E.A. Lee, Software Synthesis from Dataflow Graphs, Kluwer Academic Publishers, 1996.
18. A. Aho, R. Sethi, and J. Ullman, Compilers: Principles, Techniques, and Tools, Addison Wesley, 1988.
19. J. Fabri, Automatic Storage Optimization, UMI Press, 1982.
20. G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw Hill, 1994.
21. E. De Greef, F. Catthoor, and H. De Man, "Array Placement for Storage Size Reduction in Embedded Multimedia Systems," in Proceedings of the International Conference on Application Specific Systems, Architectures, and Processors, July 1997, pp. 66-75.
22. I. Verbauwhede, F. Catthoor, J. Vandewalle, and H. De Man, "in-Place Memory Management of Algebraic Algorithms on Application Specific ICs," Journal of VLSI Signal Processing, vol. 3, no. 3, 1991, pp. 193-200.
23. S. Ritz, M. Pankert, and H. Meyr, "Optimum Vectorization of Scalable Synchronous Dataflow Graphs," in Proceedings of the International Conference on Application Specific Array Processors, Oct. 1993, pp. 285-296.
24. J.T. Buck, S. Ha, D.G. Messerschmitt, and E.A. Lee, "Multirate Signal Processing in Ptolemy," in Proceedings of the International Conference on Acoustics, Speech, and Signal Processing, April 1991, pp. 1245-1248.
25. F. J. Harris, "Multirate FIR Filters for Interpolating and Desampling," in Handbook of Digital Signal Processing, Academic Press, 1987.
26. G. Bilsen, M. Engels, R. Lauwereins, and J.A. Peperstraete, "Cyclo-Static Dataflow," IEEE Transactions on Signal Processing, vol. 44, no. 2, 1996, pp. 397-408.
27. J. Vanhoof, I. Bolsens, and H. De Man, "Compiling Multi-Dimensional Data Streams into Distributed DSP ASIC Memory," in Proceedings of the International Conference on Computer-Aided Design, Nov. 1991. pp. 272-275.
28. P. Feautrier, Scheduling Kahn Process Networks. Technical report, ENS Lyon, 2002.
29. A. Darte, R. Schreiber, and G. Villard, "Lattice-Based Memory Allocation," in Proceedings of the International Conference on Compilers, Architecture, and Synthesis of Embedded Systems, 2003.
30. S.S. Bhattacharyya and P.K. Murthy, "The CBP Parameter - A Useful Annotation to Aid Block Diagram Compilers for DSP," in Proceedings of the International Symposium on Circuits and Systems, Geneva, Switzerland, 2000, pp. IV-209-IV-212.
31. E.A. Lee and D.G. Messerschmitt, "Static Scheduling of Synchronous Dataflow Programs for Digital Signal Processing," IEEE Trans. on Computers, vol. C-36, no. 1, 1987, pp. 24-35.
32. The Almagest, Ptolemy Reference Manual, http://ptolemy.eecs.berkeley.edu/ .
33. P.P. Vaidyanathan, Multirate Systems and Filter Banks. Prentice Hall, 1993.
34. P.K. Murthy and E.A. Lee, "Multidimensional Synchronous Dataflow," IEEE Transactions on Signal Processing, vol. 50, no. 8, 2002, pp. 2064-2079.
35. S. Ritz, M. Willems, and H. Meyr, "Scheduling for Optimum Data Memory Compaction in Block Diagram Oriented Software Synthesis," in Proceedings of the International Conference on Acoustics, Speech, and Signal Processing, 1995, pp. 2651-2654.
36. V. Zivojnovic, S. Ritz, and H. Meyr, "Retiming of DSP Programs for Optimum Vectorization," in Proceedings of the International Conference on Acoustics, Speech, and Signal Processing, April 1994, pp. 492-496.
37. I. Hong and M. Potkonjak, "Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors," Journal of Design Automation for Embedded Systems, vol. 4, no. 4, 1999, pp. 311-328.
38. S.S. Bhattacharyya, J.T. Buck, S. Ha, and E.A. Lee, "Generating Compact Code from Dataflow Specifications of Multirate Signal Processing Algorithms," IEEE Transactions on Circuits and Systems - I: Fundamental Theory and Applications, vol. 42, no. 3, 1995, pp. 138-150.