Scalable parallel memory architectures for video coding

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 38, Issue 2, 2004, Pages 173-199

  Tanskanen, Jarno K ^a   Niittylahti, Jarkko T ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

Data alignment; H.263; MPEG 4; Parallel memory access; Subword parallelism; Video coding

Indexed keywords

DATA ALIGNMENT; PARALLEL MEMORY ACCESS; SUBWORD PARALLELISM;

COMPUTER ARCHITECTURE; COSINE TRANSFORMS; DATA STORAGE EQUIPMENT; DATA TRANSFER; DIGITAL SIGNAL PROCESSING; MICROPROCESSOR CHIPS;

IMAGE CODING;

EID: 4444286061     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: 10.1023/B:VLSI.0000040428.04740.fe     Document Type: Article

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