Refining the SAT decision ordering for bounded model checking

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 535-538

  Wang, Chao ^a   Jin, HoonSang ^a   Hachtel, Gary D ^a   Somenzi, Fabio ^a  

^a UCB 450   (United States)

Author keywords

Bounded Model checking; Decision heuristic; SAT

Indexed keywords

COMPUTER SIMULATION; DECISION THEORY; ENCODING (SYMBOLS); GRAPH THEORY; HEURISTIC METHODS; ITERATIVE METHODS; PROBLEM SOLVING; RANDOM PROCESSES;

BINARY DECISION DIAGRAMS (BDD); BOUNDED MODEL CHECKING; DECISION HEURISTIC; SAT;

BOOLEAN FUNCTIONS;

EID: 4444266801     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996713     Document Type: Conference Paper

References (18)

1. A. Biere, A. Cimatti, E. Clarke, and Y. Zhu. Symbolic model checking without BDDs. In Fifth International Conference on Tools and Algorithms for Construction and Analysis of Systems, pages 193-207, Mar. 1999. LNCS 1579.
2. R. K. Brayton et al. VIS: A system for verification and synthesis. In Eighth Conference on Computer Aided Verification, pages 428-432. July 1996. LNCS 1102.
3. P. Chauhan, E. Clarke, J. Kukula, S. Sapra, H. Veith, and D. Wang. Automated abstraction refinement for model checking large state spaces using SAT based conflict analysis. In Formal Methods in Computer Aided Design, pages 33-51. Nov. 2002. LNCS 2517.
4. M. Davis, O. Logemann, and D. Loveland. A machine program for theorem proving. Communications of the ACM, 5:394-397, 1962.
5. N. Eén and N. Sörensson. Temporal induction by incremental SAT solving. Electronic Notes in Theoretical Computer Science, 89(4), 2003. First International Workshop on Bounded Model Checking.
6. M. K. Ganai, P. Ashar, A. Gupta, L. Zhang, and S. Malik. Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver. In Proceedings of the Design Automation Conference, pages 747-750, June 2002.
7. E. Goldberg and Y. Novikov. BerkMin: A fast and robust SAT-solver. In Design, Automation and Test in Europe (DATE'02), pages 142-149, Mar. 2002.
8. E. Goldberg and Y. Novikov. Verification of proofs of unsatisfiability for CNF formulas. In Design, Automation and Test in Europe (DATE'03), pages 886-891, Munich, Germany, Mar. 2003.
9. A. Gupta, M. Ganai, C. Wang, Z. Yang, and P. Ashar. Learning from BDDs in SAT-based bounded model checking. In Proceedings of the Design Automation Conference, pages 824-829, June 2003.
10. IBM Formal Verification Benchmarks. URL: http://www.haifa.il.ibm.com/projects/verification/RB_Homepage/benchmarks.html.
11. F. Lu, L. Wang, K. Cheng, J. Moondanos, and Z. Hanna. A signal correlation guided ATPG solver and its applications for solving difficult industrial cases. In Proceedings of the Design Automation Conference, pages 436-441, June 2003.
12. M. Moskewicz, C. F. Madigan, Y. Zhao, L. Zhang, and S. Malik. Chaff: Engineering an efficient SAT solver. In Proceedings of the Design Automation Conference, pages 530-535, June 2001.
13. O. Shtrichman. Tuning sat checkers for bounded model checking. In Twelfth Conference on Computer Aided Verification. July 2000. LNCS 1855.
14. J. P. M. Silva. The impact of branching heuristics in prepositional satisfiability algorithms. In Proceedings of the 9th Portuguese Conference on Artificial Intelligence, Sept. 1999.
15. J. P. M. Silva and K. A. Sakallah. Grasp - a new search algorithm for satisfiability. In Proceedings of the International Conference on Computer-Aided Design, pages 220-227, Nov. 1996.
16. URL: http://vlsi.colorado.edu/~vis.
17. J. Whittemore, J. Kim, and K. Sakallah. SATIRE: A new incremental satisfiability engine. In Proceedings of the Design Automation Conference, pages 542-545, June 2001.
18. L. Zhang and S. Malik. Validating SAT solvers using an independent resolution-based checker: Practical implementations and other applications. In Design, Automation and Test in Europe (DATE'03), pages 880-885, Mar. 2003.