Temporal induction by incremental SAT solving

Electronic Notes in Theoretical Computer Science

Volumn 89, Issue 4, 2003, Pages 543-560

  Eén, Niklas ^a   Sörensson, Niklas ^a  

^a CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

ACCIDENT PREVENTION; BOOLEAN ALGEBRA; COMPUTER HARDWARE; CONSTRAINT THEORY; MATHEMATICAL MODELS; SET THEORY;

BOOLEAN DOMAINS; FINITE STATE MACHINES (FSM); SAT PROBLEMS; SUBFORMULAS;

PROBLEM SOLVING;

EID: 4444262244     PISSN: 15710661     EISSN: None     Source Type: Journal    
DOI: 10.1016/S1571-0661(05)82542-3     Document Type: Conference Paper

References (18)

1. J. Baumgartner, A. Kuehlmann, J. Abraham "Property Checking via Structural Analysis" in CAV 2002, LNCS:2404, Springer-Verlag.
2. Bjesse P., Claessen K. "SAT-based Verification without State Space Traversal" FMCAD 2000. 1954;Springer-Verlag. LNCS
3. Biere A., Cimatti A., Clarke E.M., Zhu Y. "Symbolic model checking without BDDs" TACAS 1999. 1579;Springer, LNCS
4. A. Biere, E.M. Clarke, R. Raimi, and Y. Zhu. "Verifying safety properties of a PowerPC[tm] microprocessor using symbolic model checking without BDDs" in CAV 1999, LNCS:1633.
5. Bryant R.E. "Graph-based algorithms for boolean function manipulation" IEEE Trans, on Computers. C-35:(8):Aug. 1986
6. Chan W., Anderson R.J., Beanie P., Burns S., Modugno F., Notkin D., Reese J.D. "Model Checking Large Software Specifications" IEEE Tran. on Software Engineering. 24:(7):Jul. 1998
7. F. Copty, L. Fix, R. Fraer, E. Giunchiglia, G. Kamhi, A. Tacchella, M.Y. Vardi. "Benefits of bounded model checking at an industrial setting" in CAV 2001, LNCS:2102.
8. Claessen K., Sheeran M. "A Tutorial on Lava: A Hardware Description and Verification System" www.cs.chalmers.se/~koen/Lava:2000
9. Davis M., Logman M., Loveland D. "A machine program for theorem proving. Communications of the ACM. vol 5:1962
10. C.A.J. van Eijk. "Sequential equivalence checking without state space traversal" in Proc. Conf. on Design, Automation and Test in Europe, 1998.
11. Hooker J.N. "Solving the Incremental Satisfiability Problem" Journal of Logic Programming. vol 15:1993
12. Kroening D., Strichman O. "Efficient Computation of Recurrence Diameters" VMCAI 2003. 2003;Springer-Verlag. LNCS:2575
13. Marques-Silva J.P., Sakallah K.A. "GRASP: A Search Algorithm for Propositional Satisfiability" IEEE Transactions on Computers. vol 48:1999
14. M.W. Moskewicz, C.F. Madigan, Y. Zhao, L. Zhang, S. Malik "Chaff: Engineering an Efficient SAT Solver" in DAC 2001.
15. Strichman O. "Tuning SAT checkers for Bounded Model Checking" CAV 2000. 1855;Springer-Verlag, LNCS
16. th Advanced Research Working Conf. on Correct Hardware Design and Verification Methods, 2001.
17. M. Sheeran, S. Singh, G. Stalmarck. "Checking safety properties using induction and a SAT-solver" in FMCAD 2000, LNCS:1954.
18. J. Whittemore, J. Kim, K. Sakallah. "SATIRE: A New Incremental Satisfiability Engine" in DAC 2001, ACM Press.