-
1
-
-
0035208991
-
ASF: A practical simulation-based methodology for the synthesis of custom analog circuits
-
Nov.
-
M. J. Krasnicki, R. Phelps, J. R. Hellums, M. McClung, R. A. Rutenbar and L. R. Carley, "ASF: A practical simulation-based methodology for the synthesis of custom analog circuits", Proc. Int. Conference Computer-Aided-Design, Nov. 2001, pp. 350-357.
-
(2001)
Proc. Int. Conference Computer-aided-design
, pp. 350-357
-
-
Krasnicki, M.J.1
Phelps, R.2
Hellums, J.R.3
McClung, M.4
Rutenbar, R.A.5
Carley, L.R.6
-
2
-
-
4444324605
-
-
Orora Design Technologies Inc.
-
Arsyn User's Manual, Orora Design Technologies Inc., 2003.
-
(2003)
Arsyn User's Manual
-
-
-
3
-
-
0024754187
-
Matching properties of MOS transistors
-
Oct.
-
M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, "Matching properties of MOS transistors", IEEE J. Solid State Circuits, vol. 24, pp. 1433-1440, Oct. 1989.
-
(1989)
IEEE J. Solid State Circuits
, vol.24
, pp. 1433-1440
-
-
Pelgrom, M.J.M.1
Duinmaijer, A.C.J.2
Welbers, A.P.G.3
-
6
-
-
0026118974
-
KOAN/ANAGRAM II: New tools for device-level analog placement and routing
-
Mar.
-
J. M. Cohn, D.J. Garrod, R. A. Rutenbar and L. R. Carley, "KOAN/ANAGRAM II: New tools for device-level analog placement and routing", IEEE J. Solid State Circuits, vol. 26, pp. 330-342, Mar. 1991.
-
(1991)
IEEE J. Solid State Circuits
, vol.26
, pp. 330-342
-
-
Cohn, J.M.1
Garrod, D.J.2
Rutenbar, R.A.3
Carley, L.R.4
-
7
-
-
0029345604
-
A performance-driven placement tool for analog integrated circuits
-
Jul.
-
K. Lampaert, G. Gielen and W. M. Sansen, "A performance-driven placement tool for analog integrated circuits", IEEE J. Solid State Circuits, vol. 30, pp. 773-780, Jul. 1995.
-
(1995)
IEEE J. Solid State Circuits
, vol.30
, pp. 773-780
-
-
Lampaert, K.1
Gielen, G.2
Sansen, W.M.3
-
8
-
-
0344012019
-
IPRAIL - Intellectual property reuse-based analog IC layout automation
-
Nov.
-
N. Jangkrajarng, S. Bhattacharya, R. Hartono, and R. Shi, "IPRAIL - Intellectual property reuse-based analog IC layout automation", Integration - The VLSI Journal, vol. 36, pp. 237-262, Nov. 2003.
-
(2003)
Integration - the VLSI Journal
, vol.36
, pp. 237-262
-
-
Jangkrajarng, N.1
Bhattacharya, S.2
Hartono, R.3
Shi, R.4
-
9
-
-
85013582474
-
Minplex - A compactor that minimizes the bounding rectangle and individual rectangles in a layo?t
-
Jun.
-
S. L. Lin and J. Allen, "Minplex - a compactor that minimizes the bounding rectangle and individual rectangles in a layo?t", Proc. IEEE/ACM Design Automation Conference, Jun. 1986, pp. 123-130.
-
(1986)
Proc. IEEE/ACM Design Automation Conference
, pp. 123-130
-
-
Lin, S.L.1
Allen, J.2
-
10
-
-
0024902637
-
An efficient algorithm for layout compaction problem with symmetry constraints
-
Nov.
-
R. Okuda, T. Sato, H. Onodera and K. Tamaru, "An efficient algorithm for layout compaction problem with symmetry constraints", Proc. Int. Conference Computer-Aided-Design, Nov. 1989, pp. 148-151.
-
(1989)
Proc. Int. Conference Computer-Aided-Design
, pp. 148-151
-
-
Okuda, R.1
Sato, T.2
Onodera, H.3
Tamaru, K.4
-
15
-
-
2442502480
-
Hierarchical extraction and verification of symmetry constraints for analog layout automation
-
Jan
-
S. Bhattacharya, N. Jangkrajarng, R. Hartono, and C-J. R. Shi, "Hierarchical extraction and verification of symmetry constraints for analog layout automation", Proc. Asia and South-Pacific Design Automation Conference, Jan 2004, pp. 400-405.
-
(2004)
Proc. Asia and South-Pacific Design Automation Conference
, pp. 400-405
-
-
Bhattacharya, S.1
Jangkrajarng, N.2
Hartono, R.3
Shi, C.-J.R.4
-
16
-
-
0027309697
-
Subgemini: Identifying subcircuits using a fast subgraph isomorphism algorithm
-
Jun.
-
M. Ohlrich, C. Ebeling, E. Ginting and L. Sather, "Subgemini: Identifying subcircuits using a fast subgraph isomorphism algorithm", Proc. IEEE/ACM Design Automation Conference, Jun. 1993, pp. 31-37.
-
(1993)
Proc. IEEE/ACM Design Automation Conference
, pp. 31-37
-
-
Ohlrich, M.1
Ebeling, C.2
Ginting, E.3
Sather, L.4
|