Hierarchical extraction and verification of symmetry constraints for analog layout automation

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2004, Pages 400-405

  Bhattacharya, Sambuddha ^a   Jangkrajarng, Nuttorn ^a   Hartono, Roy ^a   Shi, C J Richard ^a  

^a University of Washington   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER PROGRAMMING LANGUAGES; ELECTRIC NETWORK TOPOLOGY; GRAPHICAL USER INTERFACES; NETWORKS (CIRCUITS); PATTERN MATCHING; SPECIFICATIONS;

AUTOMATIC ANALOG LAYOUTS; CIRCUIT STRUCTURE; CIRCUIT-SPECIFIC INFORMATION; PATTERN-MATCHING ALGORITHMS;

INTEGRATED CIRCUIT LAYOUT;

EID: 2442502480     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, "Matching properties of MOS transistors", IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1440, Oct. 1989.
2. B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill, 2001.
3. A. Hastings, The Art of Analog Layout, Prentice Hall, 2001.
4. J. M. Cohn, DJ. Garrod, R. A. Rutenbar and L. R. Carley, "KOAN/ANAGRAM II: New tools for device-level analog placement and routing", IEEE J. Solid State Circuits, vol. 26, pp. 330-342, Mar. 1991.
5. K. Lampaert, G. Gielen and W. M. Sansen, "A performance-driven placement tool for analog integrated circuits", IEEE J. Solid State Circuits, vol. 30, pp. 773-780, Jul. 1995.
6. J. D. Conway and G. G. Schrooten, "An automatic layout generator for analog circuits", Proc. European Design Automation Conference, pp. 513-519, Mar. 1992.
7. R. Castro-Lopez, F. V. Fernandez, F. Medeiro and A. Rodriguez-Vazquez, "Generation of technology-independent retargetable analog blocks", Int. J. Analog Integrated Circuits and Signal Processing, vol. 33, pp. 157-170, Dec. 2002.
8. N. Jangkrajarng, S. Bhattacharya, R. Hartono, and C-J. R. Shi, "Automatic analog layout retargeting for new processes and device sizes", Proc. IEEE Int. Symposium Circuits and Systems, vol. 4, pp. 704-707, May 2003.
9. R. Okuda, T. Sato, H. Onodera and K. Tamara, "An efficient algorithm for layout compaction problem with symmetry constraints", Proc. Int. Conference Computer-Aided-Design, pp. 148-151, Nov. 1989.
10. Y. Bourai and C. J. R. Shi, "Symmetry detection for automatic analog layout recycling", Proc. Asian and South Pacific Design Automation Conference, pp. 5-8, Jan. 1999.
11. W. S. Scott and J. K. Ousterhout, "Magic's circuit extractor", Proc. IEEE/ACM Design Automation Conference, pp. 286-292, Jun. 1985.
12. M. Ohlrich, C. Ebeling, E. Ginting and L. Sather, "Subgemini: Identifying subcircuits using a fast subgraph isomorphism algorithm", Proc. IEEE/ACM Design Automation Conference, pp. 31-37, Jun. 1993.
13. S. L. Lin and J. Allen, "Minplex - a compactor that minimizes the bounding rectangle and individual rectangles in a layout", Proc. IEEE/ACM Design Automation Conference, pp. 123-130, Jun. 1986.
14. nd Edition, Addison-Wesley, 1984.