Soft IP core implementation of recursive least squares filter using only multplicative and additive operators

Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2007, Pages 597-600

  Lightbody, Gaye ^a   Woods, Roger ^b   Francey, Jonathan ^b  

^a UNIVERSITY OF ULSTER   (United Kingdom)

^b QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

BANDPASS FILTERS; INTELLECTUAL PROPERTY CORE; INTERNET PROTOCOLS; MAPPING;

ARITHMETIC OPERATIONS; CIRCUIT ARCHITECTURES; FILTER DESIGNS; HDL DESCRIPTION; MAPPING SYSTEMS; RECURSIVE LEAST SQUARE (RLS); SOFT IP CORE; VIRTEX-4;

COMPUTER CIRCUITS;

EID: 44149115593     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2007.4380725     Document Type: Conference Paper

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