Design of a Parameterizable Silicon Intellectual Property Core for QR-Based RLS Filtering

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 11, Issue 4, 2003, Pages 659-678

  Lightbody, Gaye ^a,b   Woods, Roger ^a   Walke, Richard ^c  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

^b Amphion Semiconductor Ltd   (United Kingdom)

^c QINETIQ   (United Kingdom)

Author keywords

Intellectual property (IP) cores; QR decomposition; Recursive least squares (RLS) filtering; Very large scale integration (VLSI) architectures

Indexed keywords

ALGORITHMS; INTELLECTUAL PROPERTY; LEAST SQUARES APPROXIMATIONS; MATHEMATICAL MODELS;

CONTROL GENERATION;

VLSI CIRCUITS;

EID: 0141750615     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.816142     Document Type: Article

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