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Volumn 51, Issue 6, 2008, Pages 807-818

A glance of technology efforts for design-for-manufacturing in nano-scale CMOS processes

Author keywords

CMOS design technology platform; Design for manufacturing (DFM); Design for yield; IC design methodology; Nano CMOS IC design

Indexed keywords


EID: 44149095261     PISSN: 10092757     EISSN: 18622836     Source Type: Journal    
DOI: 10.1007/s11432-008-0054-9     Document Type: Article
Times cited : (7)

References (9)
  • 1
    • 0034854028 scopus 로고    scopus 로고
    • IC design in high cost nanometer technologies era
    • IEEE Solid-State Society Las Vegas, NV
    • Maly W. IC design in high cost nanometer technologies era. In: Design Automation Conference. Las Vegas, NV: IEEE Solid-State Society, 2001. 9-14
    • (2001) Design Automation Conference , pp. 9-14
    • Maly, W.1
  • 2
    • 52649083363 scopus 로고    scopus 로고
    • Closing the gap between manufacturing and design
    • IEEE Solid-State Circuit Society Monterey California
    • Fichtner W, Pramanik D, Bomholt L. Closing the gap between manufacturing and design. In: 2005 Electronic Design Progress Symposium. Monterey California: IEEE Solid-State Circuit Society, 2005. 64-68
    • (2005) 2005 Electronic Design Progress Symposium , pp. 64-68
    • Fichtner, W.1    Pramanik, D.2    Bomholt, L.3
  • 3
    • 44149084564 scopus 로고    scopus 로고
    • Statistical design can increase IC yield
    • 02/24
    • Sifri J. Statistical design can increase IC yield. EETimes, 02/24/2003
    • (2003) EETimes
    • Sifri, J.1
  • 4
    • 44149122066 scopus 로고    scopus 로고
    • True design-for-manufacturability critical to 65-nm design success
    • 11/07
    • Burek D. True design-for-manufacturability critical to 65-nm design success. EETimes, 11/07/2007
    • (2007) EETimes
    • Burek, D.1
  • 6
    • 17044378430 scopus 로고    scopus 로고
    • Proactive design for manufacturing (DFM) for nanometer SoC designs
    • IEEE Solid-State Circuit Society San Jose, California
    • Guardiani C, Dragone N, McNamara P. Proactive design for manufacturing (DFM) for nanometer SoC designs. In: Proceedings of the IEEE Custom Integrated Circuits Conference. San Jose, California: IEEE Solid-State Circuit Society, 2004. 309-316
    • (2004) Proceedings of the IEEE Custom Integrated Circuits Conference , pp. 309-316
    • Guardiani, C.1    Dragone, N.2    McNamara, P.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.