DFM reality in sub-nanometer IC design

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2007, Pages 226-231

  Verghese, Nishath ^a   Hurat, Philippe ^a  

^a Clear Shape Technologies

Author keywords

[No Author keywords available]

Indexed keywords

(100) SILICON; CATASTROPHIC FAILURES; DESIGN AUTOMATION CONFERENCE (DAC); DESIGN FLOWS; DESIGN FOR MANUFACTURE (DFM); DESIGN SENSITIVITIES; EDA SOLUTIONS (CO); IC DESIGNS; MANUFACTURING VARIATIONS; PARAMETRIC FAILURES; SOUTH PACIFIC; SYSTEMATIC (CO);

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; INDUSTRIAL ENGINEERING; MECHANIZATION; PHOTOACOUSTIC EFFECT; SENSITIVITY ANALYSIS;

INTEGRATED CIRCUIT LAYOUT;

EID: 44149088458     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2007.357990     Document Type: Conference Paper

References (9)

1. J.P. de Gyvez and H.P. Tuinhout, "Threshold Voltage Mismatch and Intra-Die Leakage Current in Digital CMOS Circuits, " IEEE JSSC, 2004.
2. C. Malachowsky, (NVIDIA), Advanced Reticle Symposium, 2005
3. C.H. Rahman and P.F. Zhang, "Three-dimensional DIBL for shallow-trench isolated MOSFETs," IEEE Trans. Electron Devices, 1999.
4. P. Drennan, (Freescale Semi), WESCON 2005
5. N.S. Nagaraj, "Benchmarks for Interconnect Parasitic Resistance and Capacitance, " Proc. ISQED, 2003
6. C. Bittlestone et. al., "Nanometer Design Effects and Modeling," IEEE ISSCC Ckt Des For., 2005.
7. NEC statement, 11th June, 2003
8. th 2005
9. Philippe Hurat, Michel Cote, "A Genuine Design Manufacturability Checker for Integrated Circuit Designers", Bacus 2005