QUASI-parallel multi-path detection architecture using floating-gate-Mos- based CDMA matched filters

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2004, Pages

  Nakayama, Tomoyuki ^a   Yamasaki, Toshihiko ^a   Shibata, Tadashi ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CORRELATION METHODS; DEMODULATION; GATEWAYS (COMPUTER NETWORKS); PHASE SHIFT; SAMPLING; SIGNAL FILTERING AND PREDICTION; SIGNAL TO NOISE RATIO; SYNCHRONIZATION; TRANSISTORS; VLSI CIRCUITS; WAVE FILTERS;

BASE STATIONS; CDMA MATCHED FILTERS; MULTIPLE DELAY LOCKED LOOPS; SIGNAL SEQUENCE;

CODE DIVISION MULTIPLE ACCESS;

EID: 4344670252     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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