Low-power CDMA analog matched filters based on floating-gate technology

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2002, Pages

  Yamasaki, Toshihiko ^a   Taguchi, Teruyasu ^a   Shibata, Tadashi ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITORS; CMOS INTEGRATED CIRCUITS; CODE DIVISION MULTIPLE ACCESS; COMPUTER SIMULATION; ELECTRIC FILTERS; GATES (TRANSISTOR);

ANALOG MATCHED FILTERS; FLOATING GATE TECHNOLOGY;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036291195     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Neuron-MOS parallel associator for high-speed CDMA matched filter
2. A 2.6V, 44-MHz all digital OPSK direct-sequence spread spectrum transceiver IC
3. CCD matched filter in spread spectrum communication
4. SS demodulator using SAW device for wireless LAN applications
5. Matched filter for DS-CDMA of up to 50Mchip/s based on sampled analog signal processing
6. Novel loow-power switched current matched filter for DS-CDMA wireless communication
7. A functional MOS transistor featuring gate-level weighted sum and threshold operations
8. Fast parallel spatial filters using floating-gate transistor array