A 23mW 256-tap 8MSample/s QPSK matched filter for DS-CDMA cellular telephony using recycling integrator correlators

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 354-355

  Senderowicz, D ^a   Azuma, S ^a   Matsui, H ^a   Hara, K ^a   Kawama, S ^a   Ohta, Y ^a   Miyamoto, M ^a   Iizuka, K ^a  

^a SynchroDesign Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CAPACITORS; CELLULAR TELEPHONE SYSTEMS; CMOS INTEGRATED CIRCUITS; CODE DIVISION MULTIPLE ACCESS; COMPUTER SIMULATION; CORRELATORS; NUMERICAL ANALYSIS; QUADRATURE PHASE SHIFT KEYING; SIGNAL PROCESSING; SPURIOUS SIGNAL NOISE;

MATCHED FILTERS; RECYCLING INTEGRATOR CORRELATORS (RIC);

FIR FILTERS;

EID: 0034428195     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. SiCMOS digital matched filter (DMF); Design and fabrication of 0.8 DMF and performance evaluation of 0.2 DMF
2. Matched filter for DS-CDMA of up to 50 mchips/s based on sampled analog signal processing
3. Large-area, high-resolution detector system for use in heavy charged-particle radiotherapy