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Volumn 2, Issue , 2004, Pages

An efficient FPGA implementation of advanced encryption standard algorithm

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ARRAYS; GATES (TRANSISTOR); GATEWAYS (COMPUTER NETWORKS); MATHEMATICAL TRANSFORMATIONS; OPTIMIZATION; SIGNALING;

EID: 4344669516     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (31)

References (7)
  • 2
    • 0038011043 scopus 로고    scopus 로고
    • A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES rijndael
    • Monterey, California
    • F. X. Standaert et al., "A Methodology to Implement Block Ciphers in Reconfigurable Hardware and its Application to Fast and Compact AES Rijndael," The Field Programmable Logic Array Conference, Monterey, California , pp.216-224, 2003.
    • (2003) The Field Programmable Logic Array Conference , pp. 216-224
    • Standaert, F.X.1
  • 4
    • 0035150340 scopus 로고    scopus 로고
    • Rijndael FPGA implementation utilizing look-up tables Signal Processing Systems
    • W. McLoone and J.V. McCanny, "Rijndael FPGA implementation utilizing look-up tables Signal Processing Systems," 2007 IEEE Workshop on Signal Processing Systems, pp. 349 -360, 2001.
    • (2001) 2007 IEEE Workshop on Signal Processing Systems , pp. 349-360
    • McLoone, W.1    McCanny, J.V.2
  • 5
    • 0004502409 scopus 로고    scopus 로고
    • Comparison of the Hardware Performance of the AES Candidates using Reconfigurable Hardware
    • New York, USA, April 13-14
    • K. Gaj and P. Chodowiec, "Comparison of the Hardware Performance of the AES Candidates using Reconfigurable Hardware," The Third Advanced Encryption Standard (AES3) Candidate Conference, New York, USA, April 13-14, 2000.
    • (2000) The Third Advanced Encryption Standard (AES3) Candidate Conference
    • Gaj, K.1    Chodowiec, P.2
  • 7
    • 0004512317 scopus 로고    scopus 로고
    • An FPGA implementation and performance evaluation of the AES block cipher candidate algorithm finalists
    • New York, USA, April 13-14
    • A.J. Elbirt et al., "An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists," The Third Advanced Encryption Standard (AES3) Candidate Conference, New York, USA, April 13-14, 2000.
    • (2000) The Third Advanced Encryption Standard (AES3) Candidate Conference
    • Elbirt, A.J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.