A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2003, Pages 216-224

  Standaert, François Xavier ^a   Rouvroy, Gael ^a   Quisquater, Jean Jacques ^a   Legat, Jean Didier ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

AES RIJNDAEL; Cryptography; FPGA; High encryption rates; Reconfigurable hardware

Indexed keywords

ALGORITHMS; COMPUTER SOFTWARE; CONSTRAINT THEORY; CRYPTOGRAPHY; FIELD PROGRAMMABLE GATE ARRAYS; FREQUENCIES;

ADVANCED ENCRYPTION STANDARD; BLOCK CIPHERS; DATA ENCRYPTION STANDARD; RECONFIGURABLE HARDWARE;

COMPUTER HARDWARE;

EID: 0038011043     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/611817.611849     Document Type: Conference Paper

References (15)

1. Xilinx: Virtex 2.5V Field Programmable Gate Arrays Data Sheet, http://www.xilinx.com
2. J. Daemen and V. Rijmen, The Block Cipher RIJNDAEL, NIST's AES home page, http://www.nist.gov/aes.
3. A.J. Elbirt et al., An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists, The Third Advanced Encryption Standard (AES3) Candidate Conference, April 13-14 2000, New York, USA.
4. K. Gaj and P. Chodowiec, Comparison of the Hardware Performance of the AES Candidates using Reconfigurable Hardware, The Third Advanced Encryption Standard (AES3) Candidate Conference, April 13-14 2000, New York, USA.
5. P. Chodowiec et al, Experimental Testing of the Gigabit IPSec-Compliant Implementations of RIJNDAEL and Triple-DES Using SLAAC-1V FPGA Accelerator Board, in the proceedings of ISC 2001: Information Security Workshop, LNCS 2200, pp. 220-234, Springer-Verlag.
6. A. Dandalis et al, A Comparative Study of Performance of AES Candidates Using FPGA's, The Third Advanced Encryption Standard (AES3) Candidate Conference, April 13-14 2000, New York, USA.
7. T. Ichikawa et al, Hardware Evaluation of the AES Finalists, The Third Advanced Encryption Standard (AES3) Candidate Conference, April 13-14 2000, New York, USA.
8. O. Kwon et al, Implementation of AES and Triple-DES Cryptography using a PCI-based FPGA Board, in the proceedings of ITC-CSCC 2002: The International Technical Conference On Circuits/Systems, Computers and Communications.
9. M. McLoone and J.V. McCanny, High Performance Single Ship FPGA RIJNDAEL Algorithm Implementations, in the proceedings of CHES 2001: The Third International CHES Workshop, Lecture Notes In Computer Science, LNCS2162, pp 65-76, Springer-Verlag.
10. M. McLoone and J.V. McCanny, Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm, in the proceedings of FPL 2002: The Field Programmable Logic Conference, Lecture Notes in Computer Science, LNCS 2147, p. 152ff.
11. Helion Technology, High Performance AES (Rijndael) Cores for XILINX FPGA, http://www.heliontech.com.
12. V. Fischer and M. Drutarovsky, Two Methods of RIJNDAEL Implementation in Reconfigurable Hardware, in the proceedings of CHES 2001: The Third International CHES Workshop, Lecture Notes In Computer Science, LNCS2162, pp 65-76, Springer-Verlag.
13. A. Rudra et al, Efficient RIJNDAEL Encryption Implementation with Composite Field Arithmetic, in the proceedings of CHES 2001: The Third International CHES Workshop, Lecture Notes In Computer Science, LNCS2162, pp 65-76, Springer-Verlag.
14. A. Satoh et al, A Compact RIJNDAEL Hardware Architecture with S-Box Optimization, Advances in Cryptology - ASIACRYPT 2001, LNCS 2248, pp239-254, Springer-Verlag.
15. CAST, AES Encryption Cores. http://www.cast-inc.com.