Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 1, 2002, Pages 63-76

  Huang, Chung Hsun ^a,b   Wang, Jinn Shyan ^a,b   Huang, Yan Chao ^b  

^a IEEE   (Taiwan)

^b NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

CMOS dynamic circuit; Incrementer decrementer; Multilevel folding; Multilevel lookahead; Priority encoder

Indexed keywords

CARRY SELECT ADDER; DECREMENTERS; INCREMENTER; LOOKAHEAD SIGNALS; MULTILEVEL FOLDING TECHNIQUES; MULTILEVEL LOOKAHEAD; PRIORITY ENCODERS;

ADDERS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LOGIC CIRCUITS; PERFORMANCE; SIGNAL ENCODING;

CMOS INTEGRATED CIRCUITS;

EID: 0036175845     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.974546     Document Type: Article

References (9)

1. A flexible bit-pattern associative router for interconnection networks
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5. A high-performance encoder with priority lookahead
6. High-speed and low-power CMOS priority encoders