Investigation of a programmable threshold logic gate array

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 2002, Pages 673-676

  Kelly, P M ^a   Thompson, C J ^a   McGinnity, T M ^a   Maguire, L P ^a  

^a UNIVERSITY OF ULSTER   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL NEURAL NETWORK; CIRCUIT ARCHITECTURES; FLEXIBLE PLATFORMS; INP; POWER SUPPLY; PROGRAMMABILITY; SCALE INTEGRATED CIRCUITS;

LOGIC GATES; NETWORK ARCHITECTURE; THRESHOLD LOGIC;

NEURAL NETWORKS;

EID: 4344647648     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2002.1046258     Document Type: Conference Paper

References (6)

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3. W Prost et al EU 1ST report LOCUM No.28 844 Dec 2000.
4. K.J. Chen, K. Maezawa, M. Yamamoto, ' InP-based high performance monostable-bistable transition logic elements (MOBILEs) using integrated multiple-input resonant-tunnelling devices' IEEE Electron Device Lett., vol.17 pp 127-129, Mar. 1996.
5. G.F. Niu, K.J. Chen, R.M. Chen, G. Ruan, T. Waho, K. Maezawa, M. Yamaoto, 'Circuit modelling of programmable logic gate based on controlled quenching of series-connected negative differential resistance devices' IEEE International Symposium on Circuits and Systems', pp 1628-1631, June 1997.
6. W. Prost, U Auer, F-J. Tegude, C. Pacha, K.F. Goser, G. Janssen, T. van der Roer. 'Manufacturability and robust design of nanoelectronic logic circuits based on resonant tunnelling diodes.' International Journal of Circuit Theory & Applications, vol.28, no.6, pp.537-552 Nov.-Dec. 2000 Publisher: Wiley, UK.