A precise CMOS mismatch model for analog design from weak to strong inversion

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2004, Pages

  Serrano Gotarredona, Teresa ^a   Linares Barranco, Bernabé ^a   Velarde Ramírez, Jesús ^a  

^a Centro Informatico Cientifico de Andalucia   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC NETWORK ANALYSIS; ELECTRIC POTENTIAL; MATHEMATICAL MODELS; TRANSISTORS;

ANALOG DESIGN; PARAMETER MISMATCH MODELS; SPLITTING TRANSISTORS;

CMOS INTEGRATED CIRCUITS;

EID: 4344637744     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. T. Serrano-Gotarredona and B. Linares-Barranco, "Systematic Width-and Length Dependent CMOS Transistor Mismatch Characterization and Simulation," Analog Integrated Circuits and Signal Processing, vol 21, pp. 271-296, Kluwer Academic Publishers, 1999.
2. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching Properties of MOS Transistors," IEEE Journal of Solid State Circuits, vol. 24, No. 5, pp. 1433-1440, 1989.
3. J. Bastos, Characterization of MOS Transistor Mismatch for Analog Design, Ph. D. Dissertation, Katholieke Universiteit Leuven, 1998.
4. J. Croon, M. Rosmeulen, S. Decoutere, and W. Sansen, "An Easy-to-Use Mismatch Model for the MOS Transistor," IEEE Journal of Solid State Circuits, vol. 37, No. 8, pp. 1056-1064, August, 2002.
5. C.C. Enz, F. Krummemacher and E. A. Vittoz, "An Analytical MOS Transistor Model Valid for All Regions of Operation and Dedicated to Low-Voltage Low-Current Applications," Analog Integrated Circuits and Signal Processing Journal, vol. 8, pp 83-114, July 1995.
6. C. Galup-Montoro, M. C. Schneider and A. I. A. Cunha, "A Current-Based MOSFET Model for Integrated Circuit Design", Chapter 2 in Low-Voltage/Low-Power Integrated Circuits and Systems, edited by E. Sanchez-Sinencio and A. G. Andreou, IEEE Press, August 1998.
7. T. Serrano-Gotarredona and B. Linares-Barranco, "CMOS Transistor Mismatch Model valid from Weak to Strong Inversion," Proc. 2003 European Solid-State Circuits Conference, ESSCIRC'03, September 2003.