Modeling and implementation of twisted differential on-chip interconnects for crosstalk noise reduction

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2004, Pages

  Hatirnaz, I ^a   Leblebici, Y ^a  

^a EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; COUPLED CIRCUITS; CROSSTALK; DELAY CIRCUITS; ELECTRIC FIELDS; ELECTRIC RESISTANCE; INDUCTANCE; MICROPROCESSOR CHIPS; NOISE ABATEMENT; PARALLEL PROCESSING SYSTEMS;

GENERIC INTERCONNECTS; SIGNAL LINES; SIGNAL WAVEFORMS; SYSTEM-ON-CHIP (SOC) DESIGN;

INTERCONNECTION NETWORKS;

EID: 4344623415     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. H.B. Bakoglu, "Circuits, interconnections, and packaging for vlsi," Addison Wesley, 1990.
2. A. Ruehli, "Inductance calculations in a complex integrated circuit environment," IBM Journal of Research and Development, vol. 16, pp. 470-481, Sept. 1972.
3. Y. Massoud et al., "Managing on-chip inductive effects," IEEE Transactions on VLSI Sytems, vol. 10, pp. 799-805, December 2002.
4. I. Hatirnaz Y. Leblebici, "Twisted differential on-chip interconnect architecture for inductive/capacitive crosstalk noise cancellation," Int. Symposium on System-on-Chip, 2003.
5. J. Kim et al., "A novel twisted differential line for high-speed on-chip interconnections with reduced crosstalk," Elec. Packaging Tech. Conf., 2002.
6. K. Roy G. Zhong, C. Koh, "A twisted-bundle layout structure for minimizing inductive coupling noise," ICCAD, pp. 406-411, 2000.
7. E. Akcasu et al., "Net-an a full three dimensional parasitic interconnect distributed rcl extractor for large full-chip applications," IEDM, 1995.