Twisted differential on-chip interconnect architecture for inductive/capacitive crosstalk noise cancellation

2003 International Symposium on System-on-Chip, SoC 2003 - Proceedings

Volumn , Issue , 2003, Pages 93-96

  Hatirnaz, I ^a   Leblebici, Y ^a  

^a EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

3D SIMULATIONS; CROSSTALK NOISE; CROSSTALK NOISE REDUCTION; DIFFERENTIAL LINES; HIGH-SPEED; INTERCONNECT ARCHITECTURES; MUTUAL COUPLING; ON CHIP INTERCONNECT;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CROSSTALK; INTERCONNECTION NETWORKS; THREE DIMENSIONAL COMPUTER GRAPHICS;

PROGRAMMABLE LOGIC CONTROLLERS;

EID: 78650067170     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. H.B. Bakoglu, "Circuits, Interconnections, and Packaging for VLSI", Addison-Wesley.
2. A. Ruehli, "Inductance Calculations in a Complex Integrated Circuit Environment", IBM Journal Res. Dev., 16, No 5, pp. 470-481, September 1972.
3. Y. Massoud, et al., "Managing On-Chip Inductive Effects", IEEE Trans. on VLSI Sys., vol. 10, pp.799-805, Dec. 2002.
4. D.G. Kam, et al., "GHz Twisted Differential Line Structure on Printed Circuit Board to Minimize EMI and Crosstalk Noises", Electronic Components and Tech. Conf., 2002.
5. G. Zhong, C. Koh, K. Roy, "A Twisted-Bundle Layout Structure for Minimizing Inductive Coupling Noise", ICCAD 2000, pp. 406-411.
6. D.G. Kam, S. Ahn, S. Baek, B. Park, M. Sung, J. Kim, "A Novel Twisted Differential Line for High-Speed On-Chip Interconnections with Reduced Crosstalk", Elec. Packaging Tech. Conf., 2002.
7. M.W. Beattie, L.T. Pileggi, "Inductance 101: Modeling and Extraction", DAC, 2001.
8. E. Akcasu, et al., "NET-AN A Full Three Dimensional Parasitic Interconnect Distributed RCL Extractor For Large Full-Chip Applications", IEDM, 1995.