A SIXTEEN LEVEL SCHEME ENABLING 64MBIT FLASH MEMORY USING 16MBIT TECHNOLOGY

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 937-939

  Kencke, D L ^a   Richart, R ^b   Gag, S ^b   Banerjee, S K ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC LOSSES; LOGIC GATES; PROM; TRANSCONDUCTANCE; TRANSISTORS; VOLTAGE MEASUREMENT;

FLASH MEMORY; LOGICAL THRESHOLD VOLTAGE; NOR STACKED GATE TECHNOLOGY;

DATA STORAGE EQUIPMENT;

EID: 0030402010     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.554134     Document Type: Conference Paper

References (5)

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3. K. Takeuchi, et al, IEEE J. of Solid-state Circuits, 31:4, p. 602, 1996.
4. M. Chi and A. Bergemont, 1995 IEDM Tech. Digest, p. 271.
5. R. Shiner, et al, Proc. IRPS, p. 238, 1980.