A sub-1 V dual-threshold domino circuit using product-of-sum logic

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 259-262

  Fujii, K ^a   Douseki, T ^a   Kado, Y ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LEAKAGE CURRENTS; LOGIC GATES; MICROPROCESSOR CHIPS; MOSFET DEVICES; THRESHOLD VOLTAGE;

DOMINO CIRCUITS;

ADDERS;

EID: 0034869646     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/383082.383154     Document Type: Conference Paper

References (4)

1. A 0.5 V SIMOX-MTCMOS circuit with a 200-ps logic gate
2. A Sub-1 V triple-threshold CMOS/SIMOX circuit for active power reduction
3. Dual-threshold voltage techniques for low-power digital circuits
4. High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies