Synthesis of low-leakage PD-SOI circuits with body-biasing

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 287-290

  Casu, M R ^a   Piccinini, G ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LEAKAGE CURRENTS; MOSFET DEVICES; OPTIMIZATION; THRESHOLD VOLTAGE;

LEAKAGE POWER;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0034863404     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/383082.383170     Document Type: Conference Paper

References (13)

1. A gate-level leakage power reduction method for ultra-low power cmos circuits
2. Estimation of standby leakage power in cmos circuits considering accurate modeling of transistor stacks
3. Models and algorithms for bounds on leakage in cmos circuits
4. Dual-threshold voltage techniques for low-power digital circuits
5. A 1-V multithreshold-voltage cmos digital signal processor for mobile phone application
6. A 0.5-V mtcmos/simox logic gate
7. Design and optimization of dual-threshold circuits for low-voltage low-power applications
8. Mixed-vth (MVT) cmos circuit design methodology for low power applications
9. Transistor sizing issues and tool for multi-threshold cmos technology
10. Soi for digital cmos vlsi: Considerations and advances
11. Sol digital cmos vlsi - A design perspective