Improved FFSBM algorithm and its VLSI architecture for variable block size motion estimation of H.264

Proceedings of 2005 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2005

Volumn 2005, Issue , 2005, Pages 445-448

  Li, Zhang ^a,b   Wen, Gao ^a,b  

^a INSTITUTE OF GEOLOGY AND GEOPHYSICS   (China)

^b UNIVERSITY OF CHINESE ACADEMY OF SCIENCES   (China)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHM HARDWARE CODESIGN; BLOCK SIZE MOTION ESTIMATION; FAST FULL SEARCH BLOCK MATCHING (FFSBM); VIDEO CODING STANDARD;

ALGORITHMS; BLOCK CODES; COMPUTER ARCHITECTURE; MOTION ESTIMATION; STANDARDS; VLSI CIRCUITS;

IMAGE CODING;

EID: 33847204045     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. JVT Reference Software JM 7.3, http://iphome.hhi.de/suehring/tml/ download/
2. K.M.Yang, M.T.Sun, and L. Wu, "A family of VLSI design for the motion compensation block matching algorithm", IEEE Transactions on Circuit and System for Video Technology, vol.36, no. 10 pp. 1317-1325, Oct. 1989.
3. Nuno Roma, Leonel Sousa: "A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation" VLSI-SOC, pp:253-264, 2001.
4. SWee Yeow Yap, John V Mcanny, "A VLSI architecture for advanced video coding motion estimation"IEEE Proceeding of Application-Specific Systems, Architecture, and Processors. 2003.