High-performance RISC microprocessors

IEEE Micro

Volumn 19, Issue 4, 1999, Pages 48-55

  Choquette, Jack ^a   Gupta, Mayank ^a   McCarthy, Dominic ^a   Veenstra, Jack ^a  

^a SandCraft Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER SIMULATION; COMPUTER SOFTWARE; CONSUMER PRODUCTS; DYNAMIC RANDOM ACCESS STORAGE; EMBEDDED SYSTEMS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; INTELLECTUAL PROPERTY; REDUCED INSTRUCTION SET COMPUTING; USER INTERFACES;

HIGH PERFORMANCE RISC MICROPROCESSORS; MULTI PIPELINING; SYSTEM ON CHIP APPLICATIONS;

MICROPROCESSOR CHIPS;

EID: 0032592093     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.782567     Document Type: Article

References (3)

1. Veenstra, J.E., and R.J. Fowler, "MINT: A Front End for Efficient Simulation of Shared-Memory Multiprocessors," Proc. Second Int'l Workshop Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, IEEE Computer Society Press, Los Alamitos, Calif., ISBN 0-8186-5292-6, Jan. 1994, p. 201.
2. Yeung, N., "A Dual-Issue RISC Core for SoC Applications," Embedded Microprocessor Forum, MicroDesign Resources, Sebastopol, Calif., 1998.
3. Choquette, J., "SR1-GX: A High-End Processor with Multimedia Extensions," Embedded Microprocessor Forum, MicroDesign Resources, May 1999.