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Volumn 209, Issue C, 2008, Pages 135-148

Time Separation of Events: An Inverse Method

Author keywords

Execution time analysis; Inverse method; Time separation problem; Timing constraints

Indexed keywords

DIGITAL CIRCUITS; POLYNOMIALS; PROBLEM SOLVING; TIME DELAY;

EID: 42949169387     PISSN: 15710661     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.entcs.2008.04.008     Document Type: Article
Times cited : (4)

References (12)
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  • 2
    • 0030679983 scopus 로고    scopus 로고
    • T. Amon, G. Borriello, T. Hu, and J. Liu. Symbolic timing verification of timing diagrams using Presburger formulas. In Proc. 34th DAC, 1997
    • T. Amon, G. Borriello, T. Hu, and J. Liu. Symbolic timing verification of timing diagrams using Presburger formulas. In Proc. 34th DAC, 1997
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    • T. Burks and K. Sakallah. Min-max linear programming and the timing analysis of digital circuits. In Proc. of ICCAD, pages 152-155, 1993
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    • Efficient algorithms for approximate time separation of events
    • Chakraborty S., Dill D., and Yun K. Efficient algorithms for approximate time separation of events. Sadhana 27 2 (2002) 129-162
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    • Chakraborty, S.1    Dill, D.2    Yun, K.3
  • 6
    • 0031629742 scopus 로고    scopus 로고
    • S. Chakraborty, D. Dill, K. Yun, and K. Chang. Practical timing analysis of asynchronous circuits using time separation of events. In Proc. of IEEE Custom Integrated Circuits Conference, 1998, 1998
    • S. Chakraborty, D. Dill, K. Yun, and K. Chang. Practical timing analysis of asynchronous circuits using time separation of events. In Proc. of IEEE Custom Integrated Circuits Conference, 1998, 1998
  • 7
    • 42949148323 scopus 로고    scopus 로고
    • S. Chakraborty, P. Subrahmanyam, and D. Dill. Approximate time separation of events in practice. In Proc. of 5th ACM/IEEE Int. Workshop TAU, 1997
    • S. Chakraborty, P. Subrahmanyam, and D. Dill. Approximate time separation of events in practice. In Proc. of 5th ACM/IEEE Int. Workshop TAU, 1997
  • 8
    • 33750298076 scopus 로고    scopus 로고
    • Verification of the generic architecture of a memory circuit using parametric timed automata
    • Proc. FORMATS'06, Springer
    • Chevallier R., Encrenaz-Tiphène E., Fribourg L., and Xu W. Verification of the generic architecture of a memory circuit using parametric timed automata. Proc. FORMATS'06. LNCS volume 4202 (2006), Springer 113-127
    • (2006) LNCS , vol.4202 , pp. 113-127
    • Chevallier, R.1    Encrenaz-Tiphène, E.2    Fribourg, L.3    Xu, W.4
  • 9
    • 2442427322 scopus 로고    scopus 로고
    • R. Clariso and J. Cortadella. Verification of timed circuits with symbolic delays. In Proc. ASP-DAC, pages 628-633, 2004
    • R. Clariso and J. Cortadella. Verification of timed circuits with symbolic delays. In Proc. ASP-DAC, pages 628-633, 2004
  • 11
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    • A User Guide to HYTECH
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  • 12
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    • K. McMillan and D. Dill. Algorithms for interface timing specification. In Proc. of the IEEE Int. Conf. on Computer Design (ICCD), pages 48-51, 1992
    • K. McMillan and D. Dill. Algorithms for interface timing specification. In Proc. of the IEEE Int. Conf. on Computer Design (ICCD), pages 48-51, 1992


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.