Verification of the generic architecture of a memory circuit using parametric timed automata

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4202 LNCS, Issue , 2006, Pages 113-127

  Chevallier, Remy ^a   Encrenaz Tiph̀ne, Emmanuelle ^b   Fribourg, Laurent ^b   Xu, Weiwen ^b  

^a STMICROELECTRONICS   (France)

^b CNRS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; CONSTRAINT THEORY; LINEAR SYSTEMS; NETWORKS (CIRCUITS); STORAGE ALLOCATION (COMPUTER); TIMING CIRCUITS;

CLARISO-CORTADELLA'S PARAMETRIC METHODS; LINEAR CONSTRAINTS; PARAMETRIC TIMED AUTOMATA; SPSMALL MEMORY;

AUTOMATA THEORY;

EID: 33750298076     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11867340_9     Document Type: Conference Paper

References (18)

1. HSIM Simulator Description. In http://www.synopsys.com/products/.
2. TLL Transistor Abstraction Tool description. In http://www.transeda.com/ products/.
3. R. Alur and D.L. Dill. A theory of timed automata. Theoretical Computer Science 126, pages 183-235, 1994.
4. M. Baclet and R. Chevallier. Timed verification of the SPSMALL memory. In 1th International Conference Memory Technology and Development, pages 1-2, Giens France, 2005.
5. M. Bozga, H. Jianmin, O. Maler, and S. Yovine. Verification of asynchronous circuits using timed automata. In TPTS'02, ENTCS vol 65, 2002.
6. J.A. Brzozowski and C-J.H. Seger. Asynchronous Circuits. Springer, 1994.
7. R. Chevallier, E. Encrenaz-Tiphène, L. Fribourg, and W. Xu. Timing analysis of an embedded memory: SPSMALL. In 10th WSEAS International Conference on Circuits, Athens, Greece, 2006.
8. R. Chevallier, E. Encrenaz-Tiphène, L. Fribourg, and W. Xu. Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata. Technical Report LSV-06, Laboratory Specification and Verification, 2006.
9. R. Clariso and J. Cortadella. The octahedron abstract domain. In Proc. 11th Static Analysis Symposium (SAS), LNCS 3148, Springer, pp. 312-327, 2004.
10. R. Clariso and J. Cortadella. Verification of timed circuits with symbolic delays. In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 628-633, 2004.
11. P. Cousot and R. Cousot. Abstract interpretation: A unified lattice model for static analysis of programs by construction or approximation of fixpoints. In POPL, pp. 238-252, 1977.
12. D. Dill. Timing assumptions and verification of finite-state concurrent systems. In Automatic Verification Methods for Finite State Systems, LNCS 407, Springer, 1989.
13. N. Halbwachs. Delay analysis in synchronous programs. In CAV'93, LNCS 697, Springer, pp. 333-346, 1993.
14. T.A. Henzinger, P.-H. Ho, and H. Wong-Toi. A User Guide to HYTECH. In TACAS'95, LNCS 1019, Springer, pp-41-71, 1995.
15. K. Larsen, P. Pettersson, and W. Yi. UPPAAL in a Nutshell. International Journal on Software Tools for Technology Transfer, 1:134-152, 1997.
16. O. Maler and A. Pnueli. Timing analysis of asynchronous circuits using timed automata. In CHARME'95, LNCS 987, Springer, pp. 189-205, 1995.
17. R. Ben Salah, M. Bozga, and O. Maler. On timing analysis of combinational circuits. In FORMATS'03, LNCS 2791, Springer, pp.204-219, 2003.
18. S.Yovine. KRONOS: A verification tool for real-time systems. International Journal on Software Tools for Technology Transfer, 1:123-133, 1997.